From 8b6dfdeb203c5e10c804398b822f85df2b4b6d26 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 09:58:21 +0200 Subject: sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND register Change-Id: I212ef304a03d068232f50a71c318e2b468336339 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40791 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/ibexpeak/usb_ehci.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/southbridge/intel/ibexpeak/usb_ehci.c') diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 40ba75811d..dee25f64fb 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -30,10 +30,7 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xfc, 0x301b1728); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); access_cntl = pci_read_config8(dev, 0x80); -- cgit v1.2.3