From 12b121cdb450d96309dd96b2ccc25fc5501d2250 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 18 Aug 2019 16:33:39 +0300 Subject: southbridge/intel: Tidy up preprocessor and headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/southbridge/intel/ibexpeak/pch.h | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) (limited to 'src/southbridge/intel/ibexpeak/pch.h') diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 24a7905ed2..ee0f9ad555 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -51,29 +51,26 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) -#if !defined(__SIMPLE_DEVICE__) -#include "chip.h" -void pch_enable(struct device *dev); -#endif int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG(ELOG) -void pch_log_state(void); -#endif -#else /* __PRE_RAM__ */ void enable_smbus(void); void enable_usb_bar(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned device, unsigned address); int smbus_write_byte(unsigned device, unsigned address, u8 data); int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); +#endif + void early_thermal_init(void); void southbridge_configure_default_intmap(void); -#endif + +#ifndef __ROMCC__ +#include +void pch_enable(struct device *dev); #endif #define MAINBOARD_POWER_OFF 0 -- cgit v1.2.3