From 3b452e0a797b54a05b97725f4e4e320c51098754 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 3 Oct 2019 09:16:10 +0200 Subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock. Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/ibexpeak/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/southbridge/intel/ibexpeak/Makefile.inc') diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index f22be2453b..8c4443ce0e 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += madt.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c +romstage-y += early_pch.c romstage-y += early_smbus.c romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c -- cgit v1.2.3