From 17c59f5da533eddef5e6bb85866b6d933e7fb767 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 13 May 2018 13:38:38 +0200 Subject: sb/intel/i82870: Get rid of device_t MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use of device_t has been abandoned in ramstage. Change-Id: I751b72733de2e3bf3aebd1bc85dc83ec1c406faa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26258 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/i82870/ioapic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/i82870/ioapic.c') diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index da7da5e8c6..6c653015e2 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -9,7 +9,7 @@ static int num_p64h2_ioapics = 0; -static void p64h2_ioapic_enable(device_t dev) +static void p64h2_ioapic_enable(struct device *dev) { /* We have to enable MEM and Bus Master for IOAPIC */ uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; @@ -26,7 +26,7 @@ static void p64h2_ioapic_enable(device_t dev) * @param dev PCI bus/device/function of P64H2 IOAPIC. * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0. */ -static void p64h2_ioapic_init(device_t dev) +static void p64h2_ioapic_init(struct device *dev) { uint32_t memoryBase; int apic_index, apic_id; -- cgit v1.2.3