From f555a58abc487270d4ba42527b1b43850bd718c0 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Mon, 6 Jan 2020 19:41:42 +0200
Subject: sb/intel/common: Declare common smbus_base() and enable_smbus()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This avoids including platform-specific headers with different
filenames from common code.

Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/i82801jx/early_init.c  |  1 +
 src/southbridge/intel/i82801jx/early_smbus.c | 16 ++++++++--------
 src/southbridge/intel/i82801jx/i82801jx.h    |  1 -
 3 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'src/southbridge/intel/i82801jx')

diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c
index 87831bbd05..c10c421fe4 100644
--- a/src/southbridge/intel/i82801jx/early_init.c
+++ b/src/southbridge/intel/i82801jx/early_init.c
@@ -14,6 +14,7 @@
 
 #include <console/console.h>
 #include <device/pci_ops.h>
+#include <device/smbus_host.h>
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmbase.h>
 #include "i82801jx.h"
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index 594400f710..8e3329cd71 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -16,21 +16,23 @@
  */
 
 #include <device/pci_ops.h>
-#include <console/console.h>
 #include <device/pci_def.h>
 #include <device/smbus_host.h>
 #include "i82801jx.h"
 
-void enable_smbus(void)
+uintptr_t smbus_base(void)
 {
-	pci_devfn_t dev;
+	return SMBUS_IO_BASE;
+}
 
+int smbus_enable_iobar(uintptr_t base)
+{
 	/* Set the SMBus device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x3);
+	pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
 	/* Set SMBus I/O base. */
 	pci_write_config32(dev, SMB_BASE,
-			   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+			   base | PCI_BASE_ADDRESS_SPACE_IO);
 
 	/* Set SMBus enable. */
 	pci_write_config8(dev, HOSTC, HST_EN);
@@ -38,9 +40,7 @@ void enable_smbus(void)
 	/* Set SMBus I/O space enable. */
 	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
 
-	smbus_host_reset(SMBUS_IO_BASE);
-
-	printk(BIOS_DEBUG, "SMBus controller enabled.\n");
+	return 0;
 }
 
 int smbus_read_byte(unsigned int device, unsigned int address)
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 2c5135ebfd..abf6187552 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -225,7 +225,6 @@ static inline int lpc_is_mobile(const u16 devid)
 }
 #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
 
-void enable_smbus(void);
 #if ENV_ROMSTAGE
 int smbus_read_byte(unsigned int device, unsigned int address);
 int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
-- 
cgit v1.2.3