From 8642c659e174e3838058762e5082adc778912c02 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 21 Jun 2020 15:25:01 +0200 Subject: sb/intel/i82801jx/Makefile.inc: Sort entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sort them by stage execution order, then alphabetically. Place more complex rules at the end. Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I1b36d6c0b2e615938272d65456cf10be54f66c38 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42648 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801jx/Makefile.inc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/southbridge/intel/i82801jx') diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 253a5a1b05..8edbf4f8a2 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -5,23 +5,23 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) bootblock-y += bootblock.c bootblock-y += early_init.c -ramstage-y += i82801jx.c +romstage-y += early_init.c +romstage-y += early_smbus.c + ramstage-y += fadt.c -ramstage-y += pci.c +ramstage-y += hdaudio.c +ramstage-y += i82801jx.c ramstage-y += lpc.c +ramstage-y += pci.c ramstage-y += pcie.c -ramstage-y += usb_ehci.c ramstage-y += sata.c -ramstage-y += hdaudio.c -ramstage-y += thermal.c ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += usb_ehci.c ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c -romstage-y += early_init.c -romstage-y += early_smbus.c - endif -- cgit v1.2.3