From 780e02d1a54598f60f290e7eaba3c0456006ecce Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 29 Dec 2020 05:12:56 +0200 Subject: ACPI GNVS: Drop APIC, factor out MPEN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit APIC was not referenced anywhere in ASL. MPEN has references under boards: getac/p470, roda/rk9, roda/rk886ex. MPEN has reference also in Intel SpeedStep ASL. Replace static MPEN with detection of multiple CPUs installed. Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/i82801jx/acpi/globalnvs.asl | 4 ++-- src/southbridge/intel/i82801jx/include/soc/nvs.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/southbridge/intel/i82801jx') diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 5687eb0e0b..3d0d3b2790 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) B2SS, 8, // 0x24 - BAT2 stored status /* Processor Identification */ Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable + , 8, // 0x28 - Enabled by coreboot + , 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index d2de581aa7..4325a8c1ee 100644 --- a/src/southbridge/intel/i82801jx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -39,8 +39,8 @@ struct __packed global_nvs { u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ u8 rsvd3[3]; /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ -- cgit v1.2.3