From 16fe79048f5254661ff2342aa481cbb44657b7ff Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 12 Apr 2017 17:01:31 +0200 Subject: sb/intel/*: Use common SMBus functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/i82801jx/Kconfig | 1 + src/southbridge/intel/i82801jx/early_smbus.c | 2 +- src/southbridge/intel/i82801jx/i82801jx.h | 16 --- src/southbridge/intel/i82801jx/smbus.c | 3 +- src/southbridge/intel/i82801jx/smbus.h | 140 --------------------------- 5 files changed, 4 insertions(+), 158 deletions(-) delete mode 100644 src/southbridge/intel/i82801jx/smbus.h (limited to 'src/southbridge/intel/i82801jx') diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 3f0e5692a0..5edaf1a3ce 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -17,6 +17,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select SOUTHBRIDGE_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON_SMBUS select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index fb6c252d39..a95099298f 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -19,8 +19,8 @@ #include #include #include +#include #include "i82801jx.h" -#include "smbus.h" void enable_smbus(void) { diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index be92a8b58e..fd74d2a02f 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -147,22 +147,6 @@ #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0) -/* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (10 * 1000 * 100) - - #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 00894cf82a..bc735a35b2 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -22,7 +22,8 @@ #include #include #include -#include "smbus.h" +#include +#include "i82801jx.h" static void pch_smbus_init(device_t dev) { diff --git a/src/southbridge/intel/i82801jx/smbus.h b/src/southbridge/intel/i82801jx/smbus.h deleted file mode 100644 index 61402f77b2..0000000000 --- a/src/southbridge/intel/i82801jx/smbus.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "i82801jx.h" - -static void smbus_delay(void) -{ - inb(0x80); -} - -static int smbus_wait_until_ready(u16 smbus_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while (byte & 1); - return loops ? 0 : -1; -} - -static int smbus_wait_until_done(u16 smbus_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); - return loops ? 0 : -1; -} - -static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready(smbus_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(0, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - byte = inb(smbus_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} - -#ifndef __PRE_RAM__ -static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data) -{ - unsigned char global_status_register; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(data, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - if (global_status_register != (1 << 1)) - return SMBUS_ERROR; - - return 0; -} -#endif -- cgit v1.2.3