From 7b9c139ac26eded525980e896b354c99c08cdca7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 9 Apr 2017 20:40:39 +0200 Subject: sb/intel/i82801jx: Copy i82801ix Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/19248 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/southbridge/intel/i82801jx/pcie.c | 148 ++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 src/southbridge/intel/i82801jx/pcie.c (limited to 'src/southbridge/intel/i82801jx/pcie.c') diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c new file mode 100644 index 0000000000..502e765773 --- /dev/null +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static void pci_init(struct device *dev) +{ + u16 reg16; + u32 reg32; + struct southbridge_intel_i82801ix_config *config = dev->chip_info; + + printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); + + /* Enable Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Set Cache Line Size to 0x10 */ + // This has no effect but the OS might expect it + pci_write_config8(dev, 0x0c, 0x10); + + reg16 = pci_read_config16(dev, 0x3e); + reg16 &= ~(1 << 0); /* disable parity error response */ + reg16 |= (1 << 2); /* ISA enable */ + pci_write_config16(dev, 0x3e, reg16); + + /* Enable IO xAPIC on this PCIe port */ + reg32 = pci_read_config32(dev, 0xd8); + reg32 |= (1 << 7); + pci_write_config32(dev, 0xd8, reg32); + + /* Enable Backbone Clock Gating */ + reg32 = pci_read_config32(dev, 0xe1); + reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); + pci_write_config32(dev, 0xe1, reg32); + + /* Set VC0 transaction class */ + reg32 = pci_read_config32(dev, 0x114); + reg32 &= 0xffffff00; + reg32 |= 1; + pci_write_config32(dev, 0x114, reg32); + + /* Mask completion timeouts */ + reg32 = pci_read_config32(dev, 0x148); + reg32 |= (1 << 14); + pci_write_config32(dev, 0x148, reg32); + + /* Lock R/WO Correctable Error Mask. */ + pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154)); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, 0x06); + pci_write_config16(dev, 0x06, reg16); + reg16 = pci_read_config16(dev, 0x1e); + pci_write_config16(dev, 0x1e, reg16); + + /* Get configured ASPM state */ + const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3; + + /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ + if (apmc == PCIE_ASPM_BOTH) { + reg32 = pci_read_config32(dev, 0xe8); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xe8, reg32); + } + + /* Enable expresscard hotplug events. */ + if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + pci_write_config32(dev, 0xd8, + pci_read_config32(dev, 0xd8) + | (1 << 30)); + pci_write_config16(dev, 0x42, 0x142); + } +} + +static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + /* NOTE: 0x94 is not the default position! */ + if (!vendor || !device) { + pci_write_config32(dev, 0x94, + pci_read_config32(dev, 0)); + } else { + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static void pch_pciexp_scan_bridge(device_t dev) +{ + struct southbridge_intel_i82801ix_config *config = dev->chip_info; + + /* Normal PCIe Scan */ + pciexp_scan_bridge(dev); + + if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + intel_acpi_pcie_hotplug_scan_slot(dev->link_list); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = pcie_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pch_pciexp_scan_bridge, + .ops_pci = &pci_ops, +}; + +/* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */ +static const unsigned short pci_device_ids[] = { + 0x2940, /* Port 1 */ + 0x2942, /* Port 2 */ + 0x2944, /* Port 3 */ + 0x2946, /* Port 4 */ + 0x2948, /* Port 5 */ + 0x294a, /* Port 6 */ + 0 +}; +static const struct pci_driver ich9_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- cgit v1.2.3