From b21bffae0ce5dee5d316ad544ccc6dedbc4475a1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 01:02:28 +0200 Subject: sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801jx/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel/i82801jx/lpc.c') diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 2533d8cc72..fceeb3f80e 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -451,7 +451,7 @@ static void i82801jx_lpc_read_resources(struct device *dev) * 0x00c0 ~ 0x00de....ISA DMA * 0x00c1 ~ 0x00df....ISA DMA aliases * 0x00f0.............Coprocessor Error - * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit) + * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit) * 0x04d0 - 0x04d1....PIC * 0x0500 - 0x057f....PM (DEFAULT_PMBASE) * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE) -- cgit v1.2.3