From 0d19289e840f9c711f50a74437d1b3856222db03 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 6 Feb 2024 16:55:29 +0100 Subject: arch/x86/ioapic: use uintptr_t for IOAPIC base address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Jérémy Compostella --- src/southbridge/intel/i82801jx/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/i82801jx/lpc.c') diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 7cff33a261..0a3e26f278 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -35,9 +35,9 @@ static void i82801jx_enable_apic(struct device *dev) RCBA8(0x31ff); /* Lock maximum redirection entries (MRE), R/WO register. */ - ioapic_lock_max_vectors(VIO_APIC_VADDR); + ioapic_lock_max_vectors(IO_APIC_ADDR); - register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); } static void i82801jx_enable_serial_irqs(struct device *dev) -- cgit v1.2.3