From ca4ff25290c099152ee9b2b53df6eb0d71ef0823 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 10:29:11 +0200 Subject: sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register Change-Id: If39cdfb21fec307141593f2482e014e146d4f1f2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40795 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/i82801jx/i82801jx.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/southbridge/intel/i82801jx/i82801jx.c') diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index e55735b4a1..f3c899cad5 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -13,12 +13,8 @@ typedef struct southbridge_intel_i82801jx_config config_t; static void i82801jx_enable_device(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static void i82801jx_early_settings(const config_t *const info) -- cgit v1.2.3