From 97c8089430869c1e2016b805703adbb0b038ab2a Mon Sep 17 00:00:00 2001 From: Stefan Tauner Date: Wed, 15 Aug 2018 08:06:13 +0200 Subject: sb/intel/i82801[ij]x: do not set Chipset Initialization Register (CIR) 5 The specification updates for ICH 9 & 10 require to leave the register in its default state by reserving all of its bits. Writing to it does not seem to make a difference anyway since reading it afterwards does not reflect the write (tested on ICH10). Therefore we should omit the writes but document this fact in the code because it is easy to miss from the datasheet alone. Change-Id: Iec0d79f926a826a80b90907f7861d0cb2ca30a5b Signed-off-by: Stefan Tauner Reviewed-on: https://review.coreboot.org/28094 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801jx/i82801jx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel/i82801jx/i82801jx.c') diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index 2afe3b5e74..31df5c4d14 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -45,7 +45,7 @@ static void i82801jx_early_settings(const config_t *const info) RCBA32(RCBA_CIR9) = (RCBA32(RCBA_CIR9) & ~(0x3 << 26)) | (0x2 << 26); RCBA32(RCBA_CIR7) = (RCBA32(RCBA_CIR7) & ~(0xf << 16)) | (0x5 << 16); RCBA32(RCBA_CIR13) = (RCBA32(RCBA_CIR13) & ~(0xf << 16)) | (0x5 << 16); - RCBA32(RCBA_CIR5) |= (1 << 0); + /* RCBA32(RCBA_CIR5) |= (1 << 0); cf. Specification Update */ RCBA32(RCBA_CIR10) |= (3 << 16); } -- cgit v1.2.3