From aa990e928910e35edb115095898c4668becdf1d8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 20:08:12 +0100 Subject: sb/intel/i82801jx: Move early sb init to a common place Setting southbridge GPIO is now done after console init, which should be fine. This code is partially copied from i82801ix. Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801jx/early_init.c | 61 +++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'src/southbridge/intel/i82801jx/early_init.c') diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 9d40cf2d27..469073240e 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -12,7 +12,10 @@ * GNU General Public License for more details. */ +#include #include +#include +#include #include "i82801jx.h" #include "chip.h" @@ -52,3 +55,61 @@ void i82801jx_lpc_setup(void) pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); } + +static void i82801jx_setup_bars(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + + /* Set up RCBA. */ + pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Set up PMBASE. */ + pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); + /* Enable PMBASE. */ + pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); + + /* Set up GPIOBASE. */ + pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); + /* Enable GPIO. */ + pci_write_config8(d31f0, D31F0_GPIO_CNTL, + pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); +} + +#define TCO_BASE 0x60 + +void i82801jx_early_init(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + + printk(BIOS_DEBUG, "Setting up static southbridge registers..."); + i82801jx_setup_bars(); + printk(BIOS_DEBUG, " done.\n"); + + setup_pch_gpios(&mainboard_gpio_map); + + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ + write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ + write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + printk(BIOS_DEBUG, " done.\n"); + + /* Enable IOAPIC */ + RCBA8(OIC) = 0x3; + RCBA8(OIC); + + /* Initialize power management initialization + register early as it affects reboot behavior. */ + /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 + and 0xe (required if ME is disabled but present), bit 31 locks it. + The other bits are 'must write'. */ + u8 reg8 = pci_read_config8(d31f0, 0xac); + reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); + pci_write_config8(d31f0, 0xac, reg8); + + /* TODO: If RTC power failed, reset RTC state machine + (set, then reset RTC 0x0b bit7) */ + + /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) + before they get cleared. */ +} -- cgit v1.2.3