From 7843bd560e65b0a83e99b42bdd58dd6363656c56 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:56:37 +0100 Subject: nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801jx/bootblock.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src/southbridge/intel/i82801jx/bootblock.c') diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 01faef34af..b6016793c2 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,6 +14,7 @@ */ #include +#include #include "i82801jx.h" static void enable_spi_prefetch(void) @@ -29,14 +30,14 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + i82801jx_setup_bars(); /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); + + i82801jx_lpc_setup(); } -- cgit v1.2.3