From f462b3d379198c968467053f570d6a40c9c8a715 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 20 Jan 2021 00:36:31 +0100
Subject: nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors

These accessors can be reused for several other northbridges.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/i82801ix/dmi_setup.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/southbridge/intel/i82801ix')

diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c
index cbb52c4a6c..f8b418d9df 100644
--- a/src/southbridge/intel/i82801ix/dmi_setup.c
+++ b/src/southbridge/intel/i82801ix/dmi_setup.c
@@ -2,7 +2,6 @@
 
 #include <device/pci_def.h>
 #include <console/console.h>
-#include <northbridge/intel/gm45/gm45.h>
 #include "i82801ix.h"
 
 /* VC1 Port Arbitration Table */
@@ -67,7 +66,7 @@ void i82801ix_dmi_setup(void)
 	RCBA8(RCBA_ULD + 3) = 1;
 	RCBA8(RCBA_ULD + 2) = 1;
 	/* Set target rcrb base address, i.e. DMIBAR. */
-	RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR;
+	RCBA32(RCBA_ULBA) = (uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE;
 
 	/* Enable ASPM. */
 	if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) {
-- 
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