From b21bffae0ce5dee5d316ad544ccc6dedbc4475a1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 01:02:28 +0200 Subject: sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801ix/early_smbus.c | 2 +- src/southbridge/intel/i82801ix/i82801ix.h | 2 -- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801ix/smbus.c | 2 +- 4 files changed, 3 insertions(+), 5 deletions(-) (limited to 'src/southbridge/intel/i82801ix') diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index ba0b0c81f0..6731a02fa9 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -8,7 +8,7 @@ uintptr_t smbus_base(void) { - return SMBUS_IO_BASE; + return CONFIG_FIXED_SMBUS_IO_BASE; } int smbus_enable_iobar(uintptr_t base) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 08b94c7056..ff94809cfb 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -80,8 +80,6 @@ #define D28Fx_SLCAP 0x54 -#define SMBUS_IO_BASE 0x0400 - /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 883c96428f..a2df123bc9 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -424,7 +424,7 @@ static void i82801ix_lpc_read_resources(struct device *dev) * 0x00c0 ~ 0x00de....ISA DMA * 0x00c1 ~ 0x00df....ISA DMA aliases * 0x00f0.............Coprocessor Error - * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit) + * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit) * 0x04d0 - 0x04d1....PIC * 0x0500 - 0x057f....PM (DEFAULT_PMBASE) * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE) diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index c348ed846e..815705d20a 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -49,7 +49,7 @@ static struct smbus_bus_operations lops_smbus_bus = { static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | -- cgit v1.2.3