From 36fa5b80843d836518eb89f46747e80ed6b5d96f Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Tue, 28 Oct 2014 23:43:20 +0100 Subject: i82801ix,bd82x6x,ibexpeak: rewrite expresscard hotplug This implementation is more compact, unified and works with windows as well. Tested under windows and under Debian GNU/Linux. Change-Id: I585dec12e17e22d829baa3f2dc7aecc174f9d3b5 Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/7296 Reviewed-by: Edward O'Callaghan Reviewed-by: Nicolas Reinecke Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801ix/Makefile.inc | 1 + src/southbridge/intel/i82801ix/acpi/pcie.asl | 11 ----------- src/southbridge/intel/i82801ix/chip.h | 2 ++ src/southbridge/intel/i82801ix/lpc.c | 10 ++++++++++ src/southbridge/intel/i82801ix/pcie.c | 28 +++++++++++++++++++++++++++- 5 files changed, 40 insertions(+), 12 deletions(-) (limited to 'src/southbridge/intel/i82801ix') diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 4117263ee7..a6580c4208 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -27,6 +27,7 @@ ramstage-y += sata.c ramstage-y += hdaudio.c ramstage-y += thermal.c ramstage-y += smbus.c +ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/southbridge/intel/i82801ix/acpi/pcie.asl b/src/southbridge/intel/i82801ix/acpi/pcie.asl index f02ad021c6..9233e5fa59 100644 --- a/src/southbridge/intel/i82801ix/acpi/pcie.asl +++ b/src/southbridge/intel/i82801ix/acpi/pcie.asl @@ -127,17 +127,6 @@ Device (RP04) } } - -#ifdef RP04_IS_EXPRESSCARD - Device (SLOT) - { - Name (_ADR, 0x00) - Method (_RMV, 0, NotSerialized) - { - Return (0x01) - } - } -#endif } diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 5e1221d28b..b8b58a684b 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -88,6 +88,8 @@ struct southbridge_intel_i82801ix_config { uint8_t value : 8; uint8_t scale : 2; } pcie_power_limits[6]; + + uint8_t pcie_hotplug_map[8]; }; #endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index dc2cfe8ed7..e12c724c2d 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -36,6 +36,7 @@ #include #include "i82801ix.h" #include "nvs.h" +#include #define NMI_OFF 0 @@ -555,6 +556,14 @@ static void southbridge_inject_dsdt(void) acpigen_pop_len(); } } + +static void southbridge_fill_ssdt(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + + intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); +} #endif static struct pci_operations pci_ops = { @@ -568,6 +577,7 @@ static struct device_operations device_ops = { #if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_fill_ssdt, #endif .init = lpc_init, .scan_bus = scan_static_bus, diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index 2022dac3e7..7583715add 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -24,11 +24,14 @@ #include #include #include +#include +#include "chip.h" static void pci_init(struct device *dev) { u16 reg16; u32 reg32; + struct southbridge_intel_i82801ix_config *config = dev->chip_info; printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); @@ -85,6 +88,14 @@ static void pci_init(struct device *dev) reg32 |= (1 << 1); pci_write_config32(dev, 0xe8, reg32); } + + /* Enable expresscard hotplug events. */ + if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + pci_write_config32(dev, 0xd8, + pci_read_config32(dev, 0xd8) + | (1 << 30)); + pci_write_config16(dev, 0x42, 0x142); + } } static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -99,6 +110,21 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) +{ + unsigned int ret; + struct southbridge_intel_i82801ix_config *config = dev->chip_info; + + /* Normal PCIe Scan */ + ret = pciexp_scan_bridge(dev, max); + + if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + intel_acpi_pcie_hotplug_scan_slot(dev->link_list); + } + + return ret; +} + static struct pci_operations pci_ops = { .set_subsystem = pcie_set_subsystem, }; @@ -108,7 +134,7 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, - .scan_bus = pciexp_scan_bridge, + .scan_bus = pch_pciexp_scan_bridge, .ops_pci = &pci_ops, }; -- cgit v1.2.3