From 6740647cfd2d8ff8840d1e2ab37b66ce14b19180 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 8 Jun 2020 11:13:42 +0200 Subject: sb/intel/i82801ix: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Ie05f484cf4b346601e6128c95ff2b27ce59b995f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42188 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801ix/pci.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/southbridge/intel/i82801ix/pci.c') diff --git a/src/southbridge/intel/i82801ix/pci.c b/src/southbridge/intel/i82801ix/pci.c index fff58fe08c..da710a3a8d 100644 --- a/src/southbridge/intel/i82801ix/pci.c +++ b/src/southbridge/intel/i82801ix/pci.c @@ -9,18 +9,14 @@ static void pci_init(struct device *dev) { u16 reg16; - u8 reg8; /* This device has no interrupt */ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, D30F0_SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - pci_write_config8(dev, D30F0_SMLT, reg8); + pci_update_config8(dev, D30F0_SMLT, 0x07, 0x04 << 3); - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, PCI_STATUS); //reg16 |= 0xf900; pci_write_config16(dev, PCI_STATUS, reg16); -- cgit v1.2.3