From 98c92570d9bb363740ae1b2cbbefc3c0f2404cb4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 11:39:58 +0100 Subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Angel Pons --- src/southbridge/intel/i82801ix/lpc.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'src/southbridge/intel/i82801ix/lpc.c') diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 24b8a27e63..d897130e42 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -137,6 +138,20 @@ static void i82801ix_gpi_routing(struct device *dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } +bool southbridge_support_c5(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info; + return config->c5_enable == 1; +} + +bool southbridge_support_c6(void) +{ + struct device *lpc_dev = __pci_0_1f_0; + struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info; + return config->c6_enable == 1; +} + static void i82801ix_power_options(struct device *dev) { u8 reg8; @@ -216,15 +231,15 @@ static void i82801ix_power_options(struct device *dev) reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only if (CONFIG(DEBUG_PERIODIC_SMI)) reg16 |= (3 << 0); // Periodic SMI every 8s - if (config->c5_enable) + if (southbridge_support_c5()) reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */ pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16); /* Set exit timings for C5/C6. */ - if (config->c5_enable) { + if (southbridge_support_c5()) { reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING); reg8 &= ~((7 << 3) | (7 << 0)); - if (config->c6_enable) + if (southbridge_support_c6()) reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#, 95-102us DPRSTP# to STP_CPU# */ else -- cgit v1.2.3