From b9d2e228b63c898383f1f6e6bd5e02b018ff31af Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 10:25:12 +0200 Subject: sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register Change-Id: I5a07a00e1183ef834d97c11268935617cfe17faa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40794 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/i82801ix/i82801ix.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/southbridge/intel/i82801ix/i82801ix.c') diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index f26d584a38..b76116d80f 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -13,12 +13,8 @@ typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_device(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static void i82801ix_early_settings(const config_t *const info) -- cgit v1.2.3