From ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 31 Aug 2016 19:22:16 +0200 Subject: src/southbridge: Code formating Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801ix/bootblock.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/southbridge/intel/i82801ix/bootblock.c') diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index e2223686ba..6252712eba 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -17,18 +17,18 @@ static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; + u8 reg8; + pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + dev = PCI_DEV(0, 0x1f, 0); - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); } static void bootblock_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetch(); } -- cgit v1.2.3