From 98c92570d9bb363740ae1b2cbbefc3c0f2404cb4 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Mon, 7 Nov 2022 11:39:58 +0100
Subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm

C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/i82801gx/lpc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'src/southbridge/intel/i82801gx')

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index fd0a203efa..69c1469b63 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/intel/speedstep.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -473,3 +474,13 @@ static const struct pci_driver ich7_lpc __pci_driver = {
 	.vendor	= PCI_VID_INTEL,
 	.devices = pci_device_ids,
 };
+
+bool southbridge_support_c5(void)
+{
+	return false;
+}
+
+bool southbridge_support_c6(void)
+{
+	return false;
+}
-- 
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