From 767de0aac753bb67f53d13c48207ade22b094a7e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 15 Nov 2019 19:19:53 +0100 Subject: sb/intel/i82801gx: Only include SPI code with SPI boot devices On devices lacking SPI boot devices there is a hefty timeout penalty on probing for flash chips and this code would not be useful anyway. Change-Id: I0bec11372ef54c1e1e611b81f7013932257f4ca6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36868 Reviewed-by: Nico Huber Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801gx/Kconfig | 2 +- src/southbridge/intel/i82801gx/lpc.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/i82801gx') diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 17ee4fcab3..bf9880ac27 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -23,7 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select COMMON_FADT select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select HAVE_INTEL_CHIPSET_LOCKDOWN diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 34250d396f..0330af0060 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -616,7 +616,8 @@ static void lpc_final(struct device *dev) if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) return; - spi_finalize_ops(); + if (CONFIG(BOOT_DEVICE_SPI_FLASH)) + spi_finalize_ops(); /* Lock SPIBAR */ SPIBAR16(0) = SPIBAR16(0) | (1 << 15); -- cgit v1.2.3