From 4513020064cc4765e723f6f3cc2b8a45a0dc6545 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 4 Jan 2019 14:23:54 +0100
Subject: cpu/intel: Use the common code to initialize the romstage timestamps
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The initial timestamps are now pushed on the stack when entering the
romstage C code.

Tested on Asus P5QC.

Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/southbridge/intel/i82801gx/bootblock.c | 14 --------------
 src/southbridge/intel/i82801gx/early_lpc.c | 11 -----------
 2 files changed, 25 deletions(-)

(limited to 'src/southbridge/intel/i82801gx')

diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index c9c19a3b78..6d65df3983 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -14,20 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "i82801gx.h"
 
-static void store_initial_timestamp(void)
-{
-	/* On i945/ICH7 we have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
@@ -43,8 +31,6 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
-
 	enable_spi_prefetch();
 
 	/* Enable RCBA */
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c
index 11da3ec4b1..a52fb8512e 100644
--- a/src/southbridge/intel/i82801gx/early_lpc.c
+++ b/src/southbridge/intel/i82801gx/early_lpc.c
@@ -15,21 +15,10 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <console/console.h>
 #include <arch/acpi.h>
 #include "i82801gx.h"
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 int southbridge_detect_s3_resume(void)
 {
 	u32 reg32;
-- 
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