From d19332ca3a68eeadcae73d5660834bcaadf02030 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 8 Jun 2020 12:32:54 +0200 Subject: sb/intel/i82801gx: Use PCI bitwise ops While we are at it, also reflow a few lines that fit in 96 characters. Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42191 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/i82801gx/usb_ehci.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'src/southbridge/intel/i82801gx/usb_ehci.c') diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index f665ab7a0a..0a66136d03 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -14,19 +14,13 @@ static void usb_ehci_init(struct device *dev) struct resource *res; u8 *base; u32 reg32; - u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR); - reg32 = pci_read_config32(dev, 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(dev, 0xdc, reg32); + pci_or_config32(dev, 0xdc, (1 << 31) | (1 << 27)); - reg32 = pci_read_config32(dev, 0xfc); - reg32 &= ~(3 << 2); - reg32 |= (2 << 2) | (1 << 29) | (1 << 17); - pci_write_config32(dev, 0xfc, reg32); + pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17)); /* Clear any pending port changes */ res = find_resource(dev, 0x10); @@ -35,9 +29,7 @@ static void usb_ehci_init(struct device *dev) write32(base + 0x24, reg32); /* workaround */ - reg8 = pci_read_config8(dev, 0x84); - reg8 |= (1 << 4); - pci_write_config8(dev, 0x84, reg8); + pci_or_config8(dev, 0x84, 1 << 4); printk(BIOS_DEBUG, "done.\n"); } -- cgit v1.2.3