From 647e385187767d63ca0d5d2b2f0f27bffecaa5a5 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Fri, 15 Jan 2016 13:44:53 +1100 Subject: sb/intel/i82801gx: Fix sata AHCI for desktop NM10/ICH7 Tested on Intel D510MO Before this patch, I was unable to get the SATA controller into AHCI mode. That is, I could never see PCI ID 8086:27c1 appearing on the bus. With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1 Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7) No regressions detected. Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f Signed-off-by: Damien Zammit Reviewed-on: https://review.coreboot.org/12923 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801gx/sata.c | 97 +++++++++++++++++++++-------------- 1 file changed, 59 insertions(+), 38 deletions(-) (limited to 'src/southbridge/intel/i82801gx/sata.c') diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 29f878dec3..f4eabe5f45 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Damien Zammit * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,14 +20,56 @@ #include #include #include "i82801gx.h" +#include "sata.h" typedef struct southbridge_intel_i82801gx_config config_t; +static u8 get_ich7_sata_ports(void) +{ + struct device *lpc; + + lpc = dev_find_slot(0, PCI_DEVFN(31, 0)); + + switch (pci_read_config16(lpc, PCI_DEVICE_ID)) { + case 0x27b0: + case 0x27b8: + return 0xf; + case 0x27b9: + case 0x27bd: + return 0x5; + case 0x27bc: + return 0x3; + default: + printk(BIOS_ERR, + "i82801gx_sata: error: cannot determine port config\n"); + return 0; + } +} + +void sata_enable(struct device *dev) +{ + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + if (config->sata_ahci) { + /* Set map to ahci */ + pci_write_config8(dev, SATA_MAP, + (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); + } else { + /* Set map to ide */ + pci_write_config8(dev, SATA_MAP, + pci_read_config8(dev, SATA_MAP) & ~0xc3); + } + + /* At this point, the new pci id will appear on the bus */ +} + static void sata_init(struct device *dev) { u32 reg32; u16 reg16; u32 *ahci_bar; + u8 ports; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -38,7 +81,8 @@ static void sata_init(struct device *dev) return; } - /* SATA configuration */ + /* Get ICH7 SATA port config */ + ports = get_ich7_sata_ports(); /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); @@ -70,13 +114,10 @@ static void sata_init(struct device *dev) pci_write_config32(dev, IDE_CONFIG, reg32); /* Combine IDE - SATA configuration */ - pci_write_config8(dev, 0x90, 0x02); + pci_write_config8(dev, SATA_MAP, 0x02); /* Port 0 & 1 enable */ - pci_write_config8(dev, 0x92, 0x0f); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, 0x5a000180); + pci_write_config8(dev, SATA_PCS, 0x0f); } else if(config->sata_ahci) { printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); /* Allow both Legacy and Native mode */ @@ -86,38 +127,18 @@ static void sata_init(struct device *dev) /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Set Sata Controller Mode. */ - pci_write_config8(dev, 0x90, 0x40); // 40=AHCI - /* In ACHI mode, bit[3:0] must always be set * (Port status is controlled through AHCI BAR) + * Different settings for different controller models. */ - pci_write_config8(dev, 0x92, 0x0f); + pci_write_config8(dev, SATA_PCS, ports); ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); ahci_bar[3] = config->sata_ports_implemented; - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, 0x1a000180); } else { printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); /* Set Sata Controller Mode. No Mapping(?) */ - pci_write_config8(dev, 0x90, 0x00); + pci_write_config8(dev, SATA_MAP, 0x00); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -153,12 +174,12 @@ static void sata_init(struct device *dev) pci_write_config32(dev, IDE_CONFIG, reg32); /* Port 0 & 1 enable XXX */ - pci_write_config8(dev, 0x92, 0x15); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, 0x1a000180); + pci_write_config8(dev, SATA_PCS, 0x15); } + /* Enable clock gating for unused ports and set initialization reg */ + pci_write_config32(dev, SATA_IR, SIF3(ports) | SIF2 | SIF1 | SCRE); + /* All configurations need this SATA initialization sequence */ pci_write_config8(dev, 0xa0, 0x40); pci_write_config8(dev, 0xa6, 0x22); @@ -179,9 +200,9 @@ static void sata_init(struct device *dev) pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); /* Sata Initialization Register */ - reg32 = pci_read_config32(dev, 0x94); - reg32 |= (1 << 30); // due to some bug - pci_write_config32(dev, 0x94, reg32); + reg32 = pci_read_config32(dev, SATA_IR); + reg32 |= SCRD; // due to some bug + pci_write_config32(dev, SATA_IR, reg32); } static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -211,11 +232,11 @@ static struct device_operations sata_ops = { static const unsigned short sata_ids[] = { 0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ + 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ 0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ + 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ /* NOTE: Any of the below are not properly supported yet. */ - 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ 0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ - 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ 0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */ 0 }; -- cgit v1.2.3