From 1234925ad77aa888fb28034251b950e1bc2fd480 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 27 Apr 2020 05:08:26 +0200 Subject: sb/intel/i82801gx: Fix 16-bit read/write PCI_COMMAND register Change-Id: I11b8743234cb1292db8c930edecf8fb5c47d63fd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40741 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801gx/ide.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/southbridge/intel/i82801gx/ide.c') diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index b6b30efea9..cc3e7409d4 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -30,8 +30,7 @@ static void ide_init(struct device *dev) enable_secondary = config->ide_enable_secondary; } - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); /* Native Capable, but not enabled. */ pci_write_config8(dev, 0x09, 0x8a); -- cgit v1.2.3