From 647e385187767d63ca0d5d2b2f0f27bffecaa5a5 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Fri, 15 Jan 2016 13:44:53 +1100 Subject: sb/intel/i82801gx: Fix sata AHCI for desktop NM10/ICH7 Tested on Intel D510MO Before this patch, I was unable to get the SATA controller into AHCI mode. That is, I could never see PCI ID 8086:27c1 appearing on the bus. With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1 Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7) No regressions detected. Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f Signed-off-by: Damien Zammit Reviewed-on: https://review.coreboot.org/12923 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801gx/i82801gx.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/southbridge/intel/i82801gx/i82801gx.c') diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index e3444582e0..6d97088106 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -18,6 +18,7 @@ #include #include #include "i82801gx.h" +#include "sata.h" #if !CONFIG_MMCONF_SUPPORT_DEFAULT #error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT @@ -31,6 +32,11 @@ void i82801gx_enable(device_t dev) reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); + + if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) { + printk(BIOS_DEBUG, "Set SATA mode early\n"); + sata_enable(dev); + } } struct chip_operations southbridge_intel_i82801gx_ops = { -- cgit v1.2.3