From b236352281405c3a6860b51af8acfd2e78c45e78 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 18:40:50 +0100 Subject: sb/intel/i82801gx: Add a function to set up BAR This removes some of the sb code in the nb. Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/southbridge/intel/i82801gx/early_init.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/southbridge/intel/i82801gx/early_init.c') diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 533aaefe14..7f5f442333 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include "i82801gx.h" #include "chip.h" @@ -50,3 +51,14 @@ void i82801gx_lpc_setup(void) pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec); pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec); } + +void i82801gx_setup_bars(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); + + pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); +} -- cgit v1.2.3