From fecf77770b8e68b9ef82021ca53c31db93736d93 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Nov 2019 14:19:04 +0100 Subject: sb/intel/i82801gx: Add common LPC decode code Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/southbridge/intel/i82801gx/chip.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/southbridge/intel/i82801gx/chip.h') diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 4e78c30db2..75b957573e 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -80,6 +80,12 @@ struct southbridge_intel_i82801gx_config { int docking_supported:1; int p_cnt_throttling_supported:1; int c3_latency; + + /* Additional LPC IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; }; #endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ -- cgit v1.2.3