From 5eb81bed2ea503aaf910430da492ed75d27ef94f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 10 Jan 2019 23:13:11 +0100 Subject: sb/intel/i82801gx: Detect if the southbridge supports AHCI This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801gx/chip.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/southbridge/intel/i82801gx/chip.h') diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index db27ef7097..8909f50bc1 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -18,6 +18,12 @@ #include +enum sata_mode { + SATA_MODE_AHCI = 0, + SATA_MODE_IDE_LEGACY_COMBINED, + SATA_MODE_IDE_PLAIN, +}; + struct southbridge_intel_i82801gx_config { /** * Interrupt Routing configuration @@ -65,7 +71,7 @@ struct southbridge_intel_i82801gx_config { uint32_t ide_legacy_combined; uint32_t ide_enable_primary; uint32_t ide_enable_secondary; - uint32_t sata_ahci; + enum sata_mode sata_mode; uint32_t sata_ports_implemented; /* Enable linear PCIe Root Port function numbers starting at zero */ -- cgit v1.2.3