From 4513020064cc4765e723f6f3cc2b8a45a0dc6545 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 4 Jan 2019 14:23:54 +0100 Subject: cpu/intel: Use the common code to initialize the romstage timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/i82801gx/bootblock.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'src/southbridge/intel/i82801gx/bootblock.c') diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index c9c19a3b78..6d65df3983 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -14,20 +14,8 @@ */ #include -#include #include "i82801gx.h" -static void store_initial_timestamp(void) -{ - /* On i945/ICH7 we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - static void enable_spi_prefetch(void) { u8 reg8; @@ -43,8 +31,6 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - enable_spi_prefetch(); /* Enable RCBA */ -- cgit v1.2.3