From 7cdcc38f292d7a8ffd285d17c848e60e41eec759 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Mon, 6 Jan 2020 19:00:31 +0200
Subject: sb/intel/common: Add smbus_host_reset()
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Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/i82801dx/early_smbus.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

(limited to 'src/southbridge/intel/i82801dx')

diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index 5e82ded6be..77b0aa084b 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -14,11 +14,9 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
-#include <southbridge/intel/common/smbus.h>
 #include <device/smbus_host.h>
 
 #include "i82801dx.h"
@@ -27,17 +25,16 @@ void enable_smbus(void)
 {
 	pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
-	printk(BIOS_DEBUG, "SMBus controller enabled\n");
 	/* set smbus iobase */
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	/* Set smbus enable */
 	pci_write_config8(dev, 0x40, 0x01);
 	/* Set smbus iospace enable */
 	pci_write_config16(dev, 0x4, 0x01);
-	/* Disable interrupt generation */
-	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+	smbus_host_reset(SMBUS_IO_BASE);
+
+	printk(BIOS_DEBUG, "SMBus controller enabled\n");
 }
 
 int smbus_read_byte(unsigned int device, unsigned int address)
-- 
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