From 9aeb69447d3839675b2cac51c3e95a4724fd9b0d Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 5 Oct 2012 21:54:38 +0200 Subject: hpet: common ACPI generation HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Dave Frodin --- src/southbridge/intel/i82801dx/lpc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/southbridge/intel/i82801dx/lpc.c') diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 768e70096b..fbf8e12228 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -233,7 +233,7 @@ static void enable_hpet(struct device *dev) u32 reg32, hpet, val; /* Set HPET base address and enable it */ - printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_ADDR); + printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS); reg32 = pci_read_config32(dev, GEN_CNTL); /* * Bit 17 is HPET enable bit. @@ -241,7 +241,7 @@ static void enable_hpet(struct device *dev) */ reg32 &= ~(3 << 15); /* Clear it */ - hpet = HPET_ADDR >> 12; + hpet = CONFIG_HPET_ADDRESS >> 12; hpet &= 0x3; reg32 |= (hpet << 15); @@ -254,7 +254,7 @@ static void enable_hpet(struct device *dev) val &= 0x7; if ((val & 0x4) && (hpet == (val & 0x3))) { - printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_ADDR); + printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS); } else { printk(BIOS_WARNING, "HPET was not enabled correctly\n"); reg32 &= ~(1 << 17); /* Clear Enable */ -- cgit v1.2.3