From 8e679f72e9e496dc84f463d56577f8edc6ab744e Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 14 Nov 2022 10:05:06 +0200 Subject: sb/intel/i82801dx: Improve LPC device early init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock. Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/i82801dx/lpc.c | 38 ------------------------------------ 1 file changed, 38 deletions(-) (limited to 'src/southbridge/intel/i82801dx/lpc.c') diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index c8447352a8..c92562aaed 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -21,20 +21,6 @@ typedef struct southbridge_intel_i82801dx_config config_t; -/** - * Enable ACPI I/O range. - * - * @param dev PCI device with ACPI and PM BAR's - */ -static void i82801dx_enable_acpi(struct device *dev) -{ - /* Set ACPI base address (I/O space). */ - pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - - /* Enable ACPI I/O range decode and ACPI power management. */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); -} - /** * Set miscellaneous static southbridge features. * @@ -155,12 +141,6 @@ static void i82801dx_power_options(struct device *dev) outl(reg32, pmbase + 0x04); } -static void gpio_init(struct device *dev) -{ - /* This should be done in romstage.c already */ - pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); -} static void i82801dx_rtc_init(struct device *dev) { @@ -197,17 +177,6 @@ static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801dx_lpc_decode_en(struct device *dev) -{ - /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. - * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. - * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. - * We also need to set the value for LPC I/F Enables Register. - */ - pci_write_config8(dev, COM_DEC, 0x10); - pci_write_config16(dev, LPC_EN, 0x300F); -} - /* ICH4 does not mention HPET in the docs, but * all ICH3 and ICH4 do have HPETs built in. */ @@ -247,7 +216,6 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { - i82801dx_enable_acpi(dev); /* IO APIC initialization. */ i82801dx_enable_ioapic(dev); @@ -259,9 +227,6 @@ static void lpc_init(struct device *dev) /* Setup power options. */ i82801dx_power_options(dev); - /* Set the state of the GPIO lines. */ - gpio_init(dev); - /* Initialize the real time clock. */ i82801dx_rtc_init(dev); @@ -271,9 +236,6 @@ static void lpc_init(struct device *dev) /* Initialize ISA DMA. */ isa_dma_init(); - /* Setup decode ports and LPC I/F enables. */ - i82801dx_lpc_decode_en(dev); - /* Initialize the High Precision Event Timers */ enable_hpet(dev); -- cgit v1.2.3