From 8702ab5ab1ee3e9f4f4d6edd7cec85ed6029aac8 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sun, 14 Mar 2010 17:01:08 +0000 Subject: ICH4 update, fix ATA init, drop SATA (chipset doesn't have SATA) fix some PCI IDs, enable USB bus mastering, add some license headers, ... LPC code needs another look, but I think we're getting there. Signed-off-by: Stefan Reinauer Acked-by: Joseph Smith git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i82801dx/i82801dx_smbus.c | 50 +++++++++++++++---------- 1 file changed, 30 insertions(+), 20 deletions(-) (limited to 'src/southbridge/intel/i82801dx/i82801dx_smbus.c') diff --git a/src/southbridge/intel/i82801dx/i82801dx_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_smbus.c index e56a67c1e0..1f7e47be95 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_smbus.c +++ b/src/southbridge/intel/i82801dx/i82801dx_smbus.c @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include "i82801dx.h" #include #include @@ -6,29 +25,18 @@ #define PM_BUS 0 #define PM_DEVFN PCI_DEVFN(0x1f,3) -#if 0 -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 -#endif - void smbus_enable(void) { unsigned char byte; /* iobase addr */ pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1); /* smbus enable */ - pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1); + pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1); /* iospace enable */ pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1); - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + /* Disable interrupt generation */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); } @@ -39,7 +47,7 @@ void smbus_setup(void) static void smbus_wait_until_ready(void) { - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { + while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { /* nop */ } } @@ -50,8 +58,8 @@ static void smbus_wait_until_done(void) do { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); } - while((byte &1) == 1); - while( (byte & ~1) == 0) { + while ((byte & 1) == 1); + while ((byte & ~1) == 0) { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); } } @@ -71,16 +79,18 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) /* set the command/address... */ outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), + SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - /* clear the data byte...*/ + /* clear the data byte... */ outb(0, SMBUS_IO_BASE + SMBHSTDAT0); /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); /* poll for transaction completion */ smbus_wait_until_done(); -- cgit v1.2.3