From b21bffae0ce5dee5d316ad544ccc6dedbc4475a1 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 3 Jul 2020 01:02:28 +0200
Subject: sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE

Make it default to 0x400, which is what the touched southbridges use.

Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/southbridge/intel/i82801dx/i82801dx.h | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src/southbridge/intel/i82801dx/i82801dx.h')

diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index cf852740f9..d5790ae13b 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -94,8 +94,6 @@ void aseg_smm_lock(void);
 #define RTC_FAILED      (1 <<2)
 
 
-#define SMBUS_IO_BASE	0x400
-
 #define PM1_STS		0x00
 #define   WAK_STS	(1 << 15)
 #define   PCIEXPWAK_STS	(1 << 14)
-- 
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