From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i82801cx/Makefile.inc | 14 +- src/southbridge/intel/i82801cx/ac97.c | 41 ++++ src/southbridge/intel/i82801cx/early_smbus.c | 134 +++++++++++ src/southbridge/intel/i82801cx/i82801cx_ac97.c | 41 ---- .../intel/i82801cx/i82801cx_early_smbus.c | 134 ----------- src/southbridge/intel/i82801cx/i82801cx_ide.c | 48 ---- src/southbridge/intel/i82801cx/i82801cx_lpc.c | 245 --------------------- src/southbridge/intel/i82801cx/i82801cx_nic.c | 21 -- src/southbridge/intel/i82801cx/i82801cx_pci.c | 30 --- src/southbridge/intel/i82801cx/i82801cx_reset.c | 9 - src/southbridge/intel/i82801cx/i82801cx_smbus.c | 83 ------- src/southbridge/intel/i82801cx/i82801cx_usb.c | 49 ----- src/southbridge/intel/i82801cx/ide.c | 48 ++++ src/southbridge/intel/i82801cx/lpc.c | 245 +++++++++++++++++++++ src/southbridge/intel/i82801cx/nic.c | 21 ++ src/southbridge/intel/i82801cx/pci.c | 30 +++ src/southbridge/intel/i82801cx/reset.c | 9 + src/southbridge/intel/i82801cx/smbus.c | 83 +++++++ src/southbridge/intel/i82801cx/usb.c | 49 +++++ 19 files changed, 667 insertions(+), 667 deletions(-) create mode 100644 src/southbridge/intel/i82801cx/ac97.c create mode 100644 src/southbridge/intel/i82801cx/early_smbus.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_ac97.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_early_smbus.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_ide.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_lpc.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_nic.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_pci.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_reset.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_smbus.c delete mode 100644 src/southbridge/intel/i82801cx/i82801cx_usb.c create mode 100644 src/southbridge/intel/i82801cx/ide.c create mode 100644 src/southbridge/intel/i82801cx/lpc.c create mode 100644 src/southbridge/intel/i82801cx/nic.c create mode 100644 src/southbridge/intel/i82801cx/pci.c create mode 100644 src/southbridge/intel/i82801cx/reset.c create mode 100644 src/southbridge/intel/i82801cx/smbus.c create mode 100644 src/southbridge/intel/i82801cx/usb.c (limited to 'src/southbridge/intel/i82801cx') diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc index 1e30c681a0..9c5c7fbc45 100644 --- a/src/southbridge/intel/i82801cx/Makefile.inc +++ b/src/southbridge/intel/i82801cx/Makefile.inc @@ -1,8 +1,8 @@ driver-y += i82801cx.c -driver-y += i82801cx_usb.c -driver-y += i82801cx_lpc.c -driver-y += i82801cx_ide.c -driver-y += i82801cx_ac97.c -#driver-y += i82801cx_nic.c -driver-y += i82801cx_pci.c -ramstage-y += i82801cx_reset.c +driver-y += usb.c +driver-y += lpc.c +driver-y += ide.c +driver-y += ac97.c +#driver-y += nic.c +driver-y += pci.c +ramstage-y += reset.c diff --git a/src/southbridge/intel/i82801cx/ac97.c b/src/southbridge/intel/i82801cx/ac97.c new file mode 100644 index 0000000000..5de44fc382 --- /dev/null +++ b/src/southbridge/intel/i82801cx/ac97.c @@ -0,0 +1,41 @@ +/* + * (C) 2003 Linux Networx + */ +#include +#include +#include +#include +#include +#include "i82801cx.h" + + +static struct device_operations ac97audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = i82801cx_enable, + .init = 0, + .scan_bus = 0, +}; + +static const struct pci_driver ac97audio_driver __pci_driver = { + .ops = &ac97audio_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO, +}; + + +static struct device_operations ac97modem_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = i82801cx_enable, + .init = 0, + .scan_bus = 0, +}; + +static const struct pci_driver ac97modem_driver __pci_driver = { + .ops = &ac97modem_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM, +}; diff --git a/src/southbridge/intel/i82801cx/early_smbus.c b/src/southbridge/intel/i82801cx/early_smbus.c new file mode 100644 index 0000000000..b62db80f9c --- /dev/null +++ b/src/southbridge/intel/i82801cx/early_smbus.c @@ -0,0 +1,134 @@ +#include +#include "i82801cx.h" + +static void enable_smbus(void) +{ + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + + print_debug("SMBus controller enabled\n"); + /* set smbus iobase */ + pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + /* Set smbus enable */ + pci_write_config8(dev, HOSTC, HST_EN); + /* Set smbus iospace enable */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + /* Disable interrupt generation */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); +} + + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +// See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html +// for a description of this function. +static int smbus_wait_until_active(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1)) { + break; + } + } while (--loops); + return loops ? 0 : -4; +} + +static int smbus_wait_until_ready(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + // !HOST_BUSY? + if ((val & 1) == 0) { + break; + } + if(loops == (SMBUS_TIMEOUT / 2)) { + // Clear status flags + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + } while(--loops); + return loops?0:-2; +} + +static int smbus_wait_until_done(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + // !HOST_BUSY? + if ( (val & 1) == 0) { + break; + } + // BYTE_DONE or SUCCESS or error? + if ((val & ~((1<<6)|(1<<0)) ) != 0 ) { + break; + } + } while(--loops); + return loops?0:-3; +} + +static int smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_control_register; + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + return -2; + } + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); + /* set to read from the specified device */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start a byte read, with interrupts disabled */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + /* poll for it to start */ + if (smbus_wait_until_active() < 0) { + return -4; + } + + /* poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return -3; + } + + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */ + + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + + // SUCCESS? + if (global_status_register != 2) { + return -1; + } + return byte; +} diff --git a/src/southbridge/intel/i82801cx/i82801cx_ac97.c b/src/southbridge/intel/i82801cx/i82801cx_ac97.c deleted file mode 100644 index 5de44fc382..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_ac97.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) 2003 Linux Networx - */ -#include -#include -#include -#include -#include -#include "i82801cx.h" - - -static struct device_operations ac97audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = i82801cx_enable, - .init = 0, - .scan_bus = 0, -}; - -static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO, -}; - - -static struct device_operations ac97modem_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = i82801cx_enable, - .init = 0, - .scan_bus = 0, -}; - -static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM, -}; diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c deleted file mode 100644 index b62db80f9c..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c +++ /dev/null @@ -1,134 +0,0 @@ -#include -#include "i82801cx.h" - -static void enable_smbus(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - print_debug("SMBus controller enabled\n"); - /* set smbus iobase */ - pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); - /* Set smbus enable */ - pci_write_config8(dev, HOSTC, HST_EN); - /* Set smbus iospace enable */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); -} - - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -// See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html -// for a description of this function. -static int smbus_wait_until_active(void) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if ((val & 1)) { - break; - } - } while (--loops); - return loops ? 0 : -4; -} - -static int smbus_wait_until_ready(void) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - // !HOST_BUSY? - if ((val & 1) == 0) { - break; - } - if(loops == (SMBUS_TIMEOUT / 2)) { - // Clear status flags - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); - } - } while(--loops); - return loops?0:-2; -} - -static int smbus_wait_until_done(void) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - // !HOST_BUSY? - if ( (val & 1) == 0) { - break; - } - // BYTE_DONE or SUCCESS or error? - if ((val & ~((1<<6)|(1<<0)) ) != 0 ) { - break; - } - } while(--loops); - return loops?0:-3; -} - -static int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready() < 0) { - return -2; - } - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); - /* set to read from the specified device */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start a byte read, with interrupts disabled */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - /* poll for it to start */ - if (smbus_wait_until_active() < 0) { - return -4; - } - - /* poll for transaction completion */ - if (smbus_wait_until_done() < 0) { - return -3; - } - - global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */ - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - // SUCCESS? - if (global_status_register != 2) { - return -1; - } - return byte; -} diff --git a/src/southbridge/intel/i82801cx/i82801cx_ide.c b/src/southbridge/intel/i82801cx/i82801cx_ide.c deleted file mode 100644 index 74c442c52c..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_ide.c +++ /dev/null @@ -1,48 +0,0 @@ -#include -#include -#include -#include -#include -#include "i82801cx.h" - - -static void ide_init(struct device *dev) -{ - /* Enable ide devices so the linux ide driver will work */ - uint16_t ideTimingConfig; - int enable_primary = 1; - int enable_secondary = 1; - - ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); - ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (enable_primary) { - /* Enable first ide interface */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE0 "); - } - pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); - - ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); - ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (enable_secondary) { - /* Enable secondary ide interface */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE1 "); - } - pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .enable = i82801cx_enable, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_IDE, -}; diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c deleted file mode 100644 index a1ffb8f540..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) 2003 Linux Networx, SuSE Linux AG - * (C) 2004 Tyan Computer - * (c) 2005 Digital Design Corporation - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "i82801cx.h" - -#define NMI_OFF 0 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - - -static void i82801cx_enable_ioapic( struct device *dev) -{ - uint32_t dword; - volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR; - volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10); - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */ - dword |= (1 <<13); /* coprocessor error enable */ - dword |= (1 << 1); /* delay transaction enable */ - dword |= (1 << 2); /* DMA collection buf enable */ - pci_write_config32(dev, GEN_CNTL, dword); - printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); - - // Must program the APIC's ID before using it - - *ioapic_index = 0; // Select APIC ID register - *ioapic_data = (2<<24); - - // Hang if the ID didn't take (chip not present?) - *ioapic_index = 0; - dword = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF); - if(dword != (2<<24)) - die(""); - - *ioapic_index = 3; // Select Boot Configuration register - *ioapic_data = 1; // Use Processor System Bus to deliver interrupts -} - -// This is how interrupts are received from the Super I/O chip -static void i82801cx_enable_serial_irqs( struct device *dev) -{ - // Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); -} - -/** - * Route all DMA channels to either PCI or LPC. - * - * @param dev TODO - * @param mask Identifies whether each channel should be used for PCI DMA - * (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. - * Channel 4 is not used (reserved). - */ -static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) -{ - uint16_t dmaConfig; - int channelIndex; - - dmaConfig = pci_read_config16(dev, PCI_DMA_CFG); - dmaConfig &= 0x300; // Preserve reserved bits - for(channelIndex = 0; channelIndex < 8; channelIndex++) { - if (channelIndex == 4) - continue; // Register doesn't support channel 4 - dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2); - } - pci_write_config16(dev, PCI_DMA_CFG, dmaConfig); -} - -static void i82801cx_rtc_init(struct device *dev) -{ - uint32_t dword; - int rtc_failed; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3); - - rtc_failed = pmcon3 & RTC_BATTERY_DEAD; - if (rtc_failed) { - // Clear the RTC_BATTERY_DEAD bit, but preserve - // the RTC_POWER_FAILED, G3 state, and reserved bits - // NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits - pmcon3 &= ~RTC_POWER_FAILED; - } - - get_option(&pwr_on, "power_on_after_fail"); - pmcon3 &= ~SLEEP_AFTER_POWER_FAIL; - if (!pwr_on) { - pmcon3 |= SLEEP_AFTER_POWER_FAIL; - } - pci_write_config8(dev, GEN_PMCON_3, pmcon3); - printk(BIOS_INFO, "set power %s after power fail\n", - pwr_on ? "on" : "off"); - - // See if the Safe Mode jumper is set - dword = pci_read_config32(dev, GEN_STS); - rtc_failed |= dword & (1 << 2); - - rtc_init(rtc_failed); -} - - -static void i82801cx_1f0_misc(struct device *dev) -{ - // Prevent LPC disabling, enable parity errors, and SERR# (System Error) - pci_write_config16(dev, PCI_COMMAND, 0x014f); - - // Set ACPI base address to 0x1100 (I/O space) - pci_write_config32(dev, PMBASE, 0x00001101); - - // Enable ACPI I/O and power management - pci_write_config8(dev, ACPI_CNTL, 0x10); - - // Set GPIO base address to 0x1180 (I/O space) - pci_write_config32(dev, GPIO_BASE, 0x00001181); - - // Enable GPIO - pci_write_config8(dev, GPIO_CNTL, 0x10); - - // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 - pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); - - // Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted. - pci_write_config8(dev, PIRQE_ROUT, 0x07); - - // Enable access to the upper 128 byte bank of CMOS RAM - pci_write_config8(dev, RTC_CONF, 0x04); - - // Decode 0x3F8-0x3FF (COM1) for COMA port, - // 0x2F8-0x2FF (COM2) for COMB - pci_write_config8(dev, COM_DEC, 0x10); - - // LPT decode defaults to 0x378-0x37F and 0x778-0x77F - // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 - - // Enable COMA, COMB, LPT, floppy; - // disable microcontroller, Super I/O, sound, gameport - pci_write_config16(dev, LPC_EN, 0x000F); -} - -static void lpc_init(struct device *dev) -{ - uint8_t byte; - int pwr_on=-1; - int nmi_option; - - /* IO APIC initialization */ - i82801cx_enable_ioapic(dev); - - i82801cx_enable_serial_irqs(dev); - - /* power after power fail */ - /* FIXME this doesn't work! */ - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - byte = pci_read_config8(dev, GEN_PMCON_3); - if (pwr_on) - byte &= ~1; // Return to S0 (boot) after power is re-applied - else - byte |= 1; // Return to S5 - pci_write_config8(dev, GEN_PMCON_3, byte); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); - - /* Set up NMI on errors */ - byte = inb(0x61); - byte &= ~(1 << 3); /* IOCHK# NMI Enable */ - byte &= ~(1 << 2); /* PCI SERR# Enable */ - outb(byte, 0x61); - byte = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - outb(byte, 0x70); - } - - /* Initialize the real time clock */ - i82801cx_rtc_init(dev); - - i82801cx_lpc_route_dma(dev, 0xff); - - /* Initialize isa dma */ - isa_dma_init(); - - i82801cx_1f0_misc(dev); -} - -static void i82801cx_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static struct device_operations lpc_ops = { - .read_resources = i82801cx_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = 0, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_LPC, -}; diff --git a/src/southbridge/intel/i82801cx/i82801cx_nic.c b/src/southbridge/intel/i82801cx/i82801cx_nic.c deleted file mode 100644 index 00ce038143..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_nic.c +++ /dev/null @@ -1,21 +0,0 @@ -#include -#include -#include -#include -#include -#include "i82801cx.h" - - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_LAN, -}; diff --git a/src/southbridge/intel/i82801cx/i82801cx_pci.c b/src/southbridge/intel/i82801cx/i82801cx_pci.c deleted file mode 100644 index 842b214fc8..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_pci.c +++ /dev/null @@ -1,30 +0,0 @@ -#include -#include -#include -#include -#include -#include "i82801cx.h" - -static void pci_init(struct device *dev) -{ - // NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F) - /* Enable pci error detecting */ - uint32_t dword = pci_read_config32(dev, PCI_COMMAND); - dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); - pci_write_config32(dev, PCI_COMMAND, dword); -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_PCI, -}; - diff --git a/src/southbridge/intel/i82801cx/i82801cx_reset.c b/src/southbridge/intel/i82801cx/i82801cx_reset.c deleted file mode 100644 index bd479de758..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_reset.c +++ /dev/null @@ -1,9 +0,0 @@ -#include -#include "i82801cx.h" - -void i82801cx_hard_reset(void) -{ - /* Try rebooting through port 0xcf9 */ - // Hard reset without power cycle - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); -} diff --git a/src/southbridge/intel/i82801cx/i82801cx_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_smbus.c deleted file mode 100644 index 324f82f286..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_smbus.c +++ /dev/null @@ -1,83 +0,0 @@ -#include -#include -#include -#include "i82801cx.h" - -#define PM_BUS 0 -#define PM_DEVFN PCI_DEVFN(0x1f,3) - -void smbus_enable(void) -{ - /* iobase addr */ - pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); - /* smbus enable */ - pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN); - /* iospace enable */ - pcibios_write_config_word(PM_BUS, PM_DEVFN, PCI_COMMAND, PCI_COMMAND_IO); - - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); -} - -static void smbus_wait_until_ready(void) -{ - // Loop while HOST_BUSY - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - - // Loop while HOST_BUSY - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } - while((byte &1) == 1); - - // Wait for SUCCESS or error or BYTE_DONE - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -} - -int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) -{ - unsigned char host_status_register; - unsigned char byte; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set to read from the specified device */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - *result = byte; - return host_status_register != 0x02; // return true if !SUCCESS -} diff --git a/src/southbridge/intel/i82801cx/i82801cx_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c deleted file mode 100644 index 28cb3572e5..0000000000 --- a/src/southbridge/intel/i82801cx/i82801cx_usb.c +++ /dev/null @@ -1,49 +0,0 @@ -#include -#include -#include -#include -#include -#include "i82801cx.h" - -static void usb_init(struct device *dev) -{ - -#if 0 - uint32_t cmd; - printk(BIOS_DEBUG, "USB: Setting up controller.. "); - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - - - printk(BIOS_DEBUG, "done.\n"); -#endif - -} - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .scan_bus = 0, - .enable = i82801cx_enable, -}; - -static const struct pci_driver usb_driver_1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_USB1, -}; -static const struct pci_driver usb_driver_2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_USB2, -}; -static const struct pci_driver usb_driver_3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_USB3, -}; - diff --git a/src/southbridge/intel/i82801cx/ide.c b/src/southbridge/intel/i82801cx/ide.c new file mode 100644 index 0000000000..74c442c52c --- /dev/null +++ b/src/southbridge/intel/i82801cx/ide.c @@ -0,0 +1,48 @@ +#include +#include +#include +#include +#include +#include "i82801cx.h" + + +static void ide_init(struct device *dev) +{ + /* Enable ide devices so the linux ide driver will work */ + uint16_t ideTimingConfig; + int enable_primary = 1; + int enable_secondary = 1; + + ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + if (enable_primary) { + /* Enable first ide interface */ + ideTimingConfig |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE0 "); + } + pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); + + ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + if (enable_secondary) { + /* Enable secondary ide interface */ + ideTimingConfig |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE1 "); + } + pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, + .enable = i82801cx_enable, +}; + +static const struct pci_driver ide_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_IDE, +}; diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c new file mode 100644 index 0000000000..a1ffb8f540 --- /dev/null +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -0,0 +1,245 @@ +/* + * (C) 2003 Linux Networx, SuSE Linux AG + * (C) 2004 Tyan Computer + * (c) 2005 Digital Design Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "i82801cx.h" + +#define NMI_OFF 0 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 + + +static void i82801cx_enable_ioapic( struct device *dev) +{ + uint32_t dword; + volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR; + volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10); + + dword = pci_read_config32(dev, GEN_CNTL); + dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */ + dword |= (1 <<13); /* coprocessor error enable */ + dword |= (1 << 1); /* delay transaction enable */ + dword |= (1 << 2); /* DMA collection buf enable */ + pci_write_config32(dev, GEN_CNTL, dword); + printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); + + // Must program the APIC's ID before using it + + *ioapic_index = 0; // Select APIC ID register + *ioapic_data = (2<<24); + + // Hang if the ID didn't take (chip not present?) + *ioapic_index = 0; + dword = *ioapic_data; + printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF); + if(dword != (2<<24)) + die(""); + + *ioapic_index = 3; // Select Boot Configuration register + *ioapic_data = 1; // Use Processor System Bus to deliver interrupts +} + +// This is how interrupts are received from the Super I/O chip +static void i82801cx_enable_serial_irqs( struct device *dev) +{ + // Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); +} + +/** + * Route all DMA channels to either PCI or LPC. + * + * @param dev TODO + * @param mask Identifies whether each channel should be used for PCI DMA + * (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. + * Channel 4 is not used (reserved). + */ +static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) +{ + uint16_t dmaConfig; + int channelIndex; + + dmaConfig = pci_read_config16(dev, PCI_DMA_CFG); + dmaConfig &= 0x300; // Preserve reserved bits + for(channelIndex = 0; channelIndex < 8; channelIndex++) { + if (channelIndex == 4) + continue; // Register doesn't support channel 4 + dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2); + } + pci_write_config16(dev, PCI_DMA_CFG, dmaConfig); +} + +static void i82801cx_rtc_init(struct device *dev) +{ + uint32_t dword; + int rtc_failed; + int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3); + + rtc_failed = pmcon3 & RTC_BATTERY_DEAD; + if (rtc_failed) { + // Clear the RTC_BATTERY_DEAD bit, but preserve + // the RTC_POWER_FAILED, G3 state, and reserved bits + // NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits + pmcon3 &= ~RTC_POWER_FAILED; + } + + get_option(&pwr_on, "power_on_after_fail"); + pmcon3 &= ~SLEEP_AFTER_POWER_FAIL; + if (!pwr_on) { + pmcon3 |= SLEEP_AFTER_POWER_FAIL; + } + pci_write_config8(dev, GEN_PMCON_3, pmcon3); + printk(BIOS_INFO, "set power %s after power fail\n", + pwr_on ? "on" : "off"); + + // See if the Safe Mode jumper is set + dword = pci_read_config32(dev, GEN_STS); + rtc_failed |= dword & (1 << 2); + + rtc_init(rtc_failed); +} + + +static void i82801cx_1f0_misc(struct device *dev) +{ + // Prevent LPC disabling, enable parity errors, and SERR# (System Error) + pci_write_config16(dev, PCI_COMMAND, 0x014f); + + // Set ACPI base address to 0x1100 (I/O space) + pci_write_config32(dev, PMBASE, 0x00001101); + + // Enable ACPI I/O and power management + pci_write_config8(dev, ACPI_CNTL, 0x10); + + // Set GPIO base address to 0x1180 (I/O space) + pci_write_config32(dev, GPIO_BASE, 0x00001181); + + // Enable GPIO + pci_write_config8(dev, GPIO_CNTL, 0x10); + + // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 + pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); + + // Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted. + pci_write_config8(dev, PIRQE_ROUT, 0x07); + + // Enable access to the upper 128 byte bank of CMOS RAM + pci_write_config8(dev, RTC_CONF, 0x04); + + // Decode 0x3F8-0x3FF (COM1) for COMA port, + // 0x2F8-0x2FF (COM2) for COMB + pci_write_config8(dev, COM_DEC, 0x10); + + // LPT decode defaults to 0x378-0x37F and 0x778-0x77F + // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 + + // Enable COMA, COMB, LPT, floppy; + // disable microcontroller, Super I/O, sound, gameport + pci_write_config16(dev, LPC_EN, 0x000F); +} + +static void lpc_init(struct device *dev) +{ + uint8_t byte; + int pwr_on=-1; + int nmi_option; + + /* IO APIC initialization */ + i82801cx_enable_ioapic(dev); + + i82801cx_enable_serial_irqs(dev); + + /* power after power fail */ + /* FIXME this doesn't work! */ + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + byte = pci_read_config8(dev, GEN_PMCON_3); + if (pwr_on) + byte &= ~1; // Return to S0 (boot) after power is re-applied + else + byte |= 1; // Return to S5 + pci_write_config8(dev, GEN_PMCON_3, byte); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); + + /* Set up NMI on errors */ + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + outb(byte, 0x70); + } + + /* Initialize the real time clock */ + i82801cx_rtc_init(dev); + + i82801cx_lpc_route_dma(dev, 0xff); + + /* Initialize isa dma */ + isa_dma_init(); + + i82801cx_1f0_misc(dev); +} + +static void i82801cx_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations lpc_ops = { + .read_resources = i82801cx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = 0, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_LPC, +}; diff --git a/src/southbridge/intel/i82801cx/nic.c b/src/southbridge/intel/i82801cx/nic.c new file mode 100644 index 0000000000..00ce038143 --- /dev/null +++ b/src/southbridge/intel/i82801cx/nic.c @@ -0,0 +1,21 @@ +#include +#include +#include +#include +#include +#include "i82801cx.h" + + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, +}; + +static const struct pci_driver nic_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_LAN, +}; diff --git a/src/southbridge/intel/i82801cx/pci.c b/src/southbridge/intel/i82801cx/pci.c new file mode 100644 index 0000000000..842b214fc8 --- /dev/null +++ b/src/southbridge/intel/i82801cx/pci.c @@ -0,0 +1,30 @@ +#include +#include +#include +#include +#include +#include "i82801cx.h" + +static void pci_init(struct device *dev) +{ + // NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F) + /* Enable pci error detecting */ + uint32_t dword = pci_read_config32(dev, PCI_COMMAND); + dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); + pci_write_config32(dev, PCI_COMMAND, dword); +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_PCI, +}; + diff --git a/src/southbridge/intel/i82801cx/reset.c b/src/southbridge/intel/i82801cx/reset.c new file mode 100644 index 0000000000..bd479de758 --- /dev/null +++ b/src/southbridge/intel/i82801cx/reset.c @@ -0,0 +1,9 @@ +#include +#include "i82801cx.h" + +void i82801cx_hard_reset(void) +{ + /* Try rebooting through port 0xcf9 */ + // Hard reset without power cycle + outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); +} diff --git a/src/southbridge/intel/i82801cx/smbus.c b/src/southbridge/intel/i82801cx/smbus.c new file mode 100644 index 0000000000..324f82f286 --- /dev/null +++ b/src/southbridge/intel/i82801cx/smbus.c @@ -0,0 +1,83 @@ +#include +#include +#include +#include "i82801cx.h" + +#define PM_BUS 0 +#define PM_DEVFN PCI_DEVFN(0x1f,3) + +void smbus_enable(void) +{ + /* iobase addr */ + pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + /* smbus enable */ + pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN); + /* iospace enable */ + pcibios_write_config_word(PM_BUS, PM_DEVFN, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); +} + +static void smbus_wait_until_ready(void) +{ + // Loop while HOST_BUSY + while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { + /* nop */ + } +} + +static void smbus_wait_until_done(void) +{ + unsigned char byte; + + // Loop while HOST_BUSY + do { + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + while((byte &1) == 1); + + // Wait for SUCCESS or error or BYTE_DONE + while( (byte & ~1) == 0) { + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } +} + +int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) +{ + unsigned char host_status_register; + unsigned char byte; + + smbus_wait_until_ready(); + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* set to read from the specified device */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + + /* poll for transaction completion */ + smbus_wait_until_done(); + + host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + + *result = byte; + return host_status_register != 0x02; // return true if !SUCCESS +} diff --git a/src/southbridge/intel/i82801cx/usb.c b/src/southbridge/intel/i82801cx/usb.c new file mode 100644 index 0000000000..28cb3572e5 --- /dev/null +++ b/src/southbridge/intel/i82801cx/usb.c @@ -0,0 +1,49 @@ +#include +#include +#include +#include +#include +#include "i82801cx.h" + +static void usb_init(struct device *dev) +{ + +#if 0 + uint32_t cmd; + printk(BIOS_DEBUG, "USB: Setting up controller.. "); + cmd = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, + cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); + + + printk(BIOS_DEBUG, "done.\n"); +#endif + +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .scan_bus = 0, + .enable = i82801cx_enable, +}; + +static const struct pci_driver usb_driver_1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_USB1, +}; +static const struct pci_driver usb_driver_2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_USB2, +}; +static const struct pci_driver usb_driver_3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_USB3, +}; + -- cgit v1.2.3