From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i82801bx/Makefile.inc | 20 +- src/southbridge/intel/i82801bx/ac97.c | 48 ++++ src/southbridge/intel/i82801bx/early_smbus.c | 60 ++++ src/southbridge/intel/i82801bx/i82801bx_ac97.c | 48 ---- .../intel/i82801bx/i82801bx_early_smbus.c | 60 ---- src/southbridge/intel/i82801bx/i82801bx_ide.c | 68 ----- src/southbridge/intel/i82801bx/i82801bx_lpc.c | 307 --------------------- src/southbridge/intel/i82801bx/i82801bx_nic.c | 39 --- src/southbridge/intel/i82801bx/i82801bx_pci.c | 55 ---- src/southbridge/intel/i82801bx/i82801bx_reset.c | 28 -- src/southbridge/intel/i82801bx/i82801bx_smbus.c | 61 ---- src/southbridge/intel/i82801bx/i82801bx_smbus.h | 98 ------- src/southbridge/intel/i82801bx/i82801bx_usb.c | 52 ---- src/southbridge/intel/i82801bx/i82801bx_watchdog.c | 55 ---- src/southbridge/intel/i82801bx/ide.c | 68 +++++ src/southbridge/intel/i82801bx/lpc.c | 307 +++++++++++++++++++++ src/southbridge/intel/i82801bx/nic.c | 39 +++ src/southbridge/intel/i82801bx/pci.c | 55 ++++ src/southbridge/intel/i82801bx/reset.c | 28 ++ src/southbridge/intel/i82801bx/smbus.c | 61 ++++ src/southbridge/intel/i82801bx/smbus.h | 98 +++++++ src/southbridge/intel/i82801bx/usb.c | 52 ++++ src/southbridge/intel/i82801bx/watchdog.c | 55 ++++ 23 files changed, 881 insertions(+), 881 deletions(-) create mode 100644 src/southbridge/intel/i82801bx/ac97.c create mode 100644 src/southbridge/intel/i82801bx/early_smbus.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_ac97.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_early_smbus.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_ide.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_lpc.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_nic.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_pci.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_reset.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_smbus.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_smbus.h delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_usb.c delete mode 100644 src/southbridge/intel/i82801bx/i82801bx_watchdog.c create mode 100644 src/southbridge/intel/i82801bx/ide.c create mode 100644 src/southbridge/intel/i82801bx/lpc.c create mode 100644 src/southbridge/intel/i82801bx/nic.c create mode 100644 src/southbridge/intel/i82801bx/pci.c create mode 100644 src/southbridge/intel/i82801bx/reset.c create mode 100644 src/southbridge/intel/i82801bx/smbus.c create mode 100644 src/southbridge/intel/i82801bx/smbus.h create mode 100644 src/southbridge/intel/i82801bx/usb.c create mode 100644 src/southbridge/intel/i82801bx/watchdog.c (limited to 'src/southbridge/intel/i82801bx') diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc index 313a0896df..b3587f2228 100644 --- a/src/southbridge/intel/i82801bx/Makefile.inc +++ b/src/southbridge/intel/i82801bx/Makefile.inc @@ -19,16 +19,16 @@ ## driver-y += i82801bx.c -driver-y += i82801bx_ac97.c -driver-y += i82801bx_ide.c -driver-y += i82801bx_lpc.c -driver-y += i82801bx_nic.c -driver-y += i82801bx_pci.c -driver-y += i82801bx_smbus.c -driver-y += i82801bx_usb.c +driver-y += ac97.c +driver-y += ide.c +driver-y += lpc.c +driver-y += nic.c +driver-y += pci.c +driver-y += smbus.c +driver-y += usb.c -ramstage-y += i82801bx_reset.c -ramstage-y += i82801bx_watchdog.c +ramstage-y += reset.c +ramstage-y += watchdog.c -romstage-y += i82801bx_early_smbus.c +romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801bx/ac97.c b/src/southbridge/intel/i82801bx/ac97.c new file mode 100644 index 0000000000..5e2acd3310 --- /dev/null +++ b/src/southbridge/intel/i82801bx/ac97.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "i82801bx.h" + +static struct device_operations ac97_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = i82801bx_enable, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO, +}; + +static const struct pci_driver i82801ba_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM, +}; diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c new file mode 100644 index 0000000000..4ff8d61cda --- /dev/null +++ b/src/southbridge/intel/i82801bx/early_smbus.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu for Tyan Computer) + * Copyright (C) 2007 Corey Osgood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "i82801bx.h" +#include "smbus.h" + +void enable_smbus(void) +{ + device_t dev; + + /* Set the SMBus device statically (D31:F3). */ + dev = PCI_DEV(0x0, 0x1f, 0x3); + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + print_debug("SMBus controller enabled\n"); +} + +int smbus_read_byte(u8 device, u8 address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} diff --git a/src/southbridge/intel/i82801bx/i82801bx_ac97.c b/src/southbridge/intel/i82801bx/i82801bx_ac97.c deleted file mode 100644 index 5e2acd3310..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_ac97.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Tyan Computer - * (Written by Yinghai Lu for Tyan Computer) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "i82801bx.h" - -static struct device_operations ac97_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = i82801bx_enable, -}; - -/* 82801BA/BAM (ICH2/ICH2-M) */ -static const struct pci_driver i82801ba_ac97_audio __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO, -}; - -static const struct pci_driver i82801ba_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM, -}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c deleted file mode 100644 index 6a2097ea14..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Tyan Computer - * (Written by Yinghai Lu for Tyan Computer) - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "i82801bx.h" -#include "i82801bx_smbus.h" - -void enable_smbus(void) -{ - device_t dev; - - /* Set the SMBus device statically (D31:F3). */ - dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - print_debug("SMBus controller enabled\n"); -} - -int smbus_read_byte(u8 device, u8 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c deleted file mode 100644 index 413984b5f4..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_ide.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Tyan Computer - * (Written by Yinghai Lu for Tyan Computer) - * Copyright (C) 2005 Digital Design Corporation - * (Written by Steven J. Magnani for Digital Design) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "i82801bx.h" - -typedef struct southbridge_intel_i82801bx_config config_t; - -static void ide_init(struct device *dev) -{ - u16 reg16; - config_t *conf = dev->chip_info; - - reg16 = pci_read_config16(dev, IDE_TIM_PRI); - reg16 &= ~IDE_DECODE_ENABLE; - if (!conf || conf->ide0_enable) - reg16 |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", - conf->ide0_enable ? "on" : "off"); - pci_write_config16(dev, IDE_TIM_PRI, reg16); - - reg16 = pci_read_config16(dev, IDE_TIM_SEC); - reg16 &= ~IDE_DECODE_ENABLE; - if (!conf || conf->ide1_enable) - reg16 |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", - conf->ide0_enable ? "on" : "off"); - pci_write_config16(dev, IDE_TIM_SEC, reg16); -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .enable = i82801bx_enable, -}; - -/* 82801BA/BAM (ICH2/ICH2-M) */ -static const struct pci_driver i82801ba_ide __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x244b, -}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c deleted file mode 100644 index 0ff44e6054..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Linux Networx - * Copyright (C) 2003 SuSE Linux AG - * Copyright (C) 2005 Tyan Computer - * (Written by Yinghai Lu for Tyan Computer) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "i82801bx.h" - -#define NMI_OFF 0 - -typedef struct southbridge_intel_i82801bx_config config_t; - -/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * - * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN) - * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above. - * 1 - The PIRQ is not routed to the 8259. - */ - -#define PIRQA 0x03 -#define PIRQB 0x04 -#define PIRQC 0x05 -#define PIRQD 0x06 -#define PIRQE 0x07 -#define PIRQF 0x09 -#define PIRQG 0x0A -#define PIRQH 0x0B - -/* - * Use 0x0ef8 for a bitmap to cover all these IRQ's. - * Use the defined IRQ values above or set mainboard - * specific IRQ values in your devicetree.cb. -*/ -static void i82801bx_enable_apic(struct device *dev) -{ - uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR; - volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10); - - /* Set ACPI base address (I/O space). */ - pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - - /* Enable ACPI I/O range decode and ACPI power management. */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ - reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ - reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ - reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ - pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - -static void i82801bx_enable_serial_irqs(struct device *dev) -{ - /* Set packet length and toggle silent mode bit. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); - /* TODO: Explain/#define the real meaning of these magic numbers. */ -} - -static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) -{ - u8 reg8; - config_t *config = dev->chip_info; - - reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA; - pci_write_config8(dev, PIRQA_ROUT, reg8); - - reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB; - pci_write_config8(dev, PIRQB_ROUT, reg8); - - reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC; - pci_write_config8(dev, PIRQC_ROUT, reg8); - - reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD; - pci_write_config8(dev, PIRQD_ROUT, reg8); - - - reg8 = (config->pirqe_routing) ? config->pirqe_routing : PIRQE; - pci_write_config8(dev, PIRQE_ROUT, reg8); - - reg8 = (config->pirqf_routing) ? config->pirqf_routing : PIRQF; - pci_write_config8(dev, PIRQF_ROUT, reg8); - - reg8 = (config->pirqg_routing) ? config->pirqg_routing : PIRQG; - pci_write_config8(dev, PIRQG_ROUT, reg8); - - reg8 = (config->pirqh_routing) ? config->pirqh_routing : PIRQH; - pci_write_config8(dev, PIRQH_ROUT, reg8); -} - -static void i82801bx_power_options(device_t dev) -{ - uint8_t byte; - int pwr_on = -1; - int nmi_option; - - /* power after power fail */ - /* FIXME this doesn't work! */ - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); - printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off"); - - /* Set up NMI on errors. */ - byte = inb(0x61); - byte &= ~(1 << 3); /* IOCHK# NMI Enable */ - byte &= ~(1 << 2); /* PCI SERR# Enable */ - outb(byte, 0x61); - byte = inb(0x70); - - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* Set NMI. */ - outb(byte, 0x70); - } -} - -static void gpio_init(device_t dev) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL, GPIO_EN); -} - -static void i82801bx_rtc_init(struct device *dev) -{ - uint8_t reg8; - uint32_t reg32; - int rtc_failed; - - reg8 = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = reg8 & RTC_BATTERY_DEAD; - if (rtc_failed) { - reg8 &= ~(1 << 1); /* Preserve the power fail state. */ - pci_write_config8(dev, GEN_PMCON_3, reg8); - } - reg32 = pci_read_config32(dev, GEN_STS); - rtc_failed |= reg32 & (1 << 2); - rtc_init(rtc_failed); - - /* Enable access to the upper 128 byte bank of CMOS RAM. */ - pci_write_config8(dev, RTC_CONF, 0x04); -} - -static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) -{ - uint16_t reg16; - int i; - - reg16 = pci_read_config16(dev, PCI_DMA_CFG); - reg16 &= 0x300; - for (i = 0; i < 8; i++) { - if (i == 4) - continue; - reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); - } - pci_write_config16(dev, PCI_DMA_CFG, reg16); -} - -static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) -{ - /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. - * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. - * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. - * We also need to set the value for LPC I/F Enables Register. - */ - pci_write_config8(dev, COM_DEC, 0x10); - pci_write_config16(dev, LPC_EN, 0x300F); -} - -static void lpc_init(struct device *dev) -{ - uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); - - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - - /* IO APIC initialization. */ - i82801bx_enable_apic(dev); - - i82801bx_enable_serial_irqs(dev); - - /* Setup the PIRQ. */ - i82801bx_pirq_init(dev, ich_model); - - /* Setup power options. */ - i82801bx_power_options(dev); - - /* Set the state of the GPIO lines. */ - gpio_init(dev); - - /* Initialize the real time clock. */ - i82801bx_rtc_init(dev); - - /* Route DMA. */ - i82801bx_lpc_route_dma(dev, 0xff); - - /* Initialize ISA DMA. */ - isa_dma_init(); - - /* Setup decode ports and LPC I/F enables. */ - i82801bx_lpc_decode_en(dev, ich_model); -} - -static void i82801bx_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static struct device_operations lpc_ops = { - .read_resources = i82801bx_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = i82801bx_enable, -}; - -/* 82801BA/BAM (ICH2/ICH2-M) */ -static const struct pci_driver i82801ba_lpc __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2440, -}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_nic.c b/src/southbridge/intel/i82801bx/i82801bx_nic.c deleted file mode 100644 index b843aca328..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_nic.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, -}; - -/* 82801BA/BAM (ICH2/ICH2-M) */ -static const struct pci_driver i82801ba_nic __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801BA_LAN, -}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_pci.c b/src/southbridge/intel/i82801bx/i82801bx_pci.c deleted file mode 100644 index 828a668197..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_pci.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Tyan Computer - * (Written by Yinghai Lu for Tyan Computer) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "i82801bx.h" - -static void pci_init(struct device *dev) -{ - u16 reg16; - - /* Clear system errors */ - reg16 = pci_read_config16(dev, PCI_STATUS); - reg16 |= 0xf900; /* Clear possible errors */ - pci_write_config16(dev, PCI_STATUS, reg16); - - reg16 = pci_read_config16(dev, SECSTS); - reg16 |= 0xf800; /* Clear possible errors */ - pci_write_config16(dev, SECSTS, reg16); -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, -}; - -/* 82801BA/BAM (ICH2/ICH2-M) */ -static const struct pci_driver i82801misc_pci __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x244e, -}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_reset.c b/src/southbridge/intel/i82801bx/i82801bx_reset.c deleted file mode 100644 index 8d85cdca75..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_reset.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2002 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -void hard_reset(void) -{ - /* Try rebooting through port 0xcf9. */ - outb((1 << 2) | (1 << 1), 0xcf9); -} diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.c b/src/southbridge/intel/i82801bx/i82801bx_smbus.c deleted file mode 100644 index db27b094c3..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_smbus.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "i82801bx.h" -#include "i82801bx_smbus.h" - -static int lsmbus_read_byte(device_t dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_read_byte(res->base, device, address); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, -}; - -static const struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = i82801bx_enable, - .ops_smbus_bus = &lops_smbus_bus, -}; - -/* 82801BA/BAM (ICH2/ICH2-M) */ -static const struct pci_driver i82801ba_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801BA_SMB, -}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h deleted file mode 100644 index c04e9dc8d3..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include - -static void smbus_delay(void) -{ - inb(0x80); -} - -static int smbus_wait_until_ready(u16 smbus_io_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while (byte & 1); - return loops ? 0 : -1; -} - -static int smbus_wait_until_done(u16 smbus_io_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); - return loops ? 0 : -1; -} - -static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_io_base + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_io_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_io_base + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(0, smbus_io_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), - smbus_io_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} diff --git a/src/southbridge/intel/i82801bx/i82801bx_usb.c b/src/southbridge/intel/i82801bx/i82801bx_usb.c deleted file mode 100644 index f90f6a6906..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_usb.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "i82801bx.h" - -static void usb_init(struct device *dev) -{ - /* TODO: Any init needed? Some ports have it, others don't. */ -} - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .scan_bus = 0, - .enable = i82801bx_enable, -}; - -/* 82801BA/BAM (ICH2/ICH2-M) */ -static const struct pci_driver i82801ba_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801BA_USB1, -}; - -static const struct pci_driver i82801ba_usb2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801BA_USB2, -}; diff --git a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c deleted file mode 100644 index cd0c20d98e..0000000000 --- a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 John Dufresne - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -/* TODO: I'm fairly sure the same functionality is provided elsewhere. */ - -void watchdog_off(void) -{ - device_t dev; - unsigned long value, base; - - /* Turn off the ICH5 watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - - /* Disable the watchdog timer. */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - - printk(BIOS_DEBUG, "ICH Watchdog disabled\n"); -} diff --git a/src/southbridge/intel/i82801bx/ide.c b/src/southbridge/intel/i82801bx/ide.c new file mode 100644 index 0000000000..413984b5f4 --- /dev/null +++ b/src/southbridge/intel/i82801bx/ide.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu for Tyan Computer) + * Copyright (C) 2005 Digital Design Corporation + * (Written by Steven J. Magnani for Digital Design) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "i82801bx.h" + +typedef struct southbridge_intel_i82801bx_config config_t; + +static void ide_init(struct device *dev) +{ + u16 reg16; + config_t *conf = dev->chip_info; + + reg16 = pci_read_config16(dev, IDE_TIM_PRI); + reg16 &= ~IDE_DECODE_ENABLE; + if (!conf || conf->ide0_enable) + reg16 |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", + conf->ide0_enable ? "on" : "off"); + pci_write_config16(dev, IDE_TIM_PRI, reg16); + + reg16 = pci_read_config16(dev, IDE_TIM_SEC); + reg16 &= ~IDE_DECODE_ENABLE; + if (!conf || conf->ide1_enable) + reg16 |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", + conf->ide0_enable ? "on" : "off"); + pci_write_config16(dev, IDE_TIM_SEC, reg16); +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, + .enable = i82801bx_enable, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x244b, +}; diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c new file mode 100644 index 0000000000..0ff44e6054 --- /dev/null +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -0,0 +1,307 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * Copyright (C) 2003 SuSE Linux AG + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "i82801bx.h" + +#define NMI_OFF 0 + +typedef struct southbridge_intel_i82801bx_config config_t; + +/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * + * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN) + * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above. + * 1 - The PIRQ is not routed to the 8259. + */ + +#define PIRQA 0x03 +#define PIRQB 0x04 +#define PIRQC 0x05 +#define PIRQD 0x06 +#define PIRQE 0x07 +#define PIRQF 0x09 +#define PIRQG 0x0A +#define PIRQH 0x0B + +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. + * Use the defined IRQ values above or set mainboard + * specific IRQ values in your devicetree.cb. +*/ +static void i82801bx_enable_apic(struct device *dev) +{ + uint32_t reg32; + volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR; + volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10); + + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + /* TODO: From i82801ca, needed/useful on other ICH? */ + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ +} + +static void i82801bx_enable_serial_irqs(struct device *dev) +{ + /* Set packet length and toggle silent mode bit. */ + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); + /* TODO: Explain/#define the real meaning of these magic numbers. */ +} + +static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) +{ + u8 reg8; + config_t *config = dev->chip_info; + + reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA; + pci_write_config8(dev, PIRQA_ROUT, reg8); + + reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB; + pci_write_config8(dev, PIRQB_ROUT, reg8); + + reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC; + pci_write_config8(dev, PIRQC_ROUT, reg8); + + reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD; + pci_write_config8(dev, PIRQD_ROUT, reg8); + + + reg8 = (config->pirqe_routing) ? config->pirqe_routing : PIRQE; + pci_write_config8(dev, PIRQE_ROUT, reg8); + + reg8 = (config->pirqf_routing) ? config->pirqf_routing : PIRQF; + pci_write_config8(dev, PIRQF_ROUT, reg8); + + reg8 = (config->pirqg_routing) ? config->pirqg_routing : PIRQG; + pci_write_config8(dev, PIRQG_ROUT, reg8); + + reg8 = (config->pirqh_routing) ? config->pirqh_routing : PIRQH; + pci_write_config8(dev, PIRQH_ROUT, reg8); +} + +static void i82801bx_power_options(device_t dev) +{ + uint8_t byte; + int pwr_on = -1; + int nmi_option; + + /* power after power fail */ + /* FIXME this doesn't work! */ + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); + printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off"); + + /* Set up NMI on errors. */ + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); + + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* Set NMI. */ + outb(byte, 0x70); + } +} + +static void gpio_init(device_t dev) +{ + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, GPIO_EN); +} + +static void i82801bx_rtc_init(struct device *dev) +{ + uint8_t reg8; + uint32_t reg32; + int rtc_failed; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~(1 << 1); /* Preserve the power fail state. */ + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + reg32 = pci_read_config32(dev, GEN_STS); + rtc_failed |= reg32 & (1 << 2); + rtc_init(rtc_failed); + + /* Enable access to the upper 128 byte bank of CMOS RAM. */ + pci_write_config8(dev, RTC_CONF, 0x04); +} + +static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) +{ + uint16_t reg16; + int i; + + reg16 = pci_read_config16(dev, PCI_DMA_CFG); + reg16 &= 0x300; + for (i = 0; i < 8; i++) { + if (i == 4) + continue; + reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); + } + pci_write_config16(dev, PCI_DMA_CFG, reg16); +} + +static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) +{ + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. + * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. + * We also need to set the value for LPC I/F Enables Register. + */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); +} + +static void lpc_init(struct device *dev) +{ + uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + i82801bx_enable_apic(dev); + + i82801bx_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + i82801bx_pirq_init(dev, ich_model); + + /* Setup power options. */ + i82801bx_power_options(dev); + + /* Set the state of the GPIO lines. */ + gpio_init(dev); + + /* Initialize the real time clock. */ + i82801bx_rtc_init(dev); + + /* Route DMA. */ + i82801bx_lpc_route_dma(dev, 0xff); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + /* Setup decode ports and LPC I/F enables. */ + i82801bx_lpc_decode_en(dev, ich_model); +} + +static void i82801bx_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations lpc_ops = { + .read_resources = i82801bx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i82801bx_enable, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2440, +}; diff --git a/src/southbridge/intel/i82801bx/nic.c b/src/southbridge/intel/i82801bx/nic.c new file mode 100644 index 0000000000..b843aca328 --- /dev/null +++ b/src/southbridge/intel/i82801bx/nic.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_LAN, +}; diff --git a/src/southbridge/intel/i82801bx/pci.c b/src/southbridge/intel/i82801bx/pci.c new file mode 100644 index 0000000000..828a668197 --- /dev/null +++ b/src/southbridge/intel/i82801bx/pci.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "i82801bx.h" + +static void pci_init(struct device *dev) +{ + u16 reg16; + + /* Clear system errors */ + reg16 = pci_read_config16(dev, PCI_STATUS); + reg16 |= 0xf900; /* Clear possible errors */ + pci_write_config16(dev, PCI_STATUS, reg16); + + reg16 = pci_read_config16(dev, SECSTS); + reg16 |= 0xf800; /* Clear possible errors */ + pci_write_config16(dev, SECSTS, reg16); +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801misc_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x244e, +}; diff --git a/src/southbridge/intel/i82801bx/reset.c b/src/southbridge/intel/i82801bx/reset.c new file mode 100644 index 0000000000..8d85cdca75 --- /dev/null +++ b/src/southbridge/intel/i82801bx/reset.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +void hard_reset(void) +{ + /* Try rebooting through port 0xcf9. */ + outb((1 << 2) | (1 << 1), 0xcf9); +} diff --git a/src/southbridge/intel/i82801bx/smbus.c b/src/southbridge/intel/i82801bx/smbus.c new file mode 100644 index 0000000000..d4a609ae3f --- /dev/null +++ b/src/southbridge/intel/i82801bx/smbus.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "i82801bx.h" +#include "smbus.h" + +static int lsmbus_read_byte(device_t dev, u8 address) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + + return do_smbus_read_byte(res->base, device, address); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .read_byte = lsmbus_read_byte, +}; + +static const struct device_operations smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .enable = i82801bx_enable, + .ops_smbus_bus = &lops_smbus_bus, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_smb __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_SMB, +}; diff --git a/src/southbridge/intel/i82801bx/smbus.h b/src/southbridge/intel/i82801bx/smbus.h new file mode 100644 index 0000000000..c04e9dc8d3 --- /dev/null +++ b/src/southbridge/intel/i82801bx/smbus.h @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +static void smbus_delay(void) +{ + inb(0x80); +} + +static int smbus_wait_until_ready(u16 smbus_io_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +static int smbus_wait_until_done(u16 smbus_io_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_io_base + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_io_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_io_base + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, smbus_io_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), + smbus_io_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} diff --git a/src/southbridge/intel/i82801bx/usb.c b/src/southbridge/intel/i82801bx/usb.c new file mode 100644 index 0000000000..f90f6a6906 --- /dev/null +++ b/src/southbridge/intel/i82801bx/usb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "i82801bx.h" + +static void usb_init(struct device *dev) +{ + /* TODO: Any init needed? Some ports have it, others don't. */ +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .scan_bus = 0, + .enable = i82801bx_enable, +}; + +/* 82801BA/BAM (ICH2/ICH2-M) */ +static const struct pci_driver i82801ba_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_USB1, +}; + +static const struct pci_driver i82801ba_usb2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_USB2, +}; diff --git a/src/southbridge/intel/i82801bx/watchdog.c b/src/southbridge/intel/i82801bx/watchdog.c new file mode 100644 index 0000000000..cd0c20d98e --- /dev/null +++ b/src/southbridge/intel/i82801bx/watchdog.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 John Dufresne + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +/* TODO: I'm fairly sure the same functionality is provided elsewhere. */ + +void watchdog_off(void) +{ + device_t dev; + unsigned long value, base; + + /* Turn off the ICH5 watchdog. */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + + /* Enable I/O space. */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Get TCO base. */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + + /* Disable the watchdog timer. */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status. */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + + printk(BIOS_DEBUG, "ICH Watchdog disabled\n"); +} -- cgit v1.2.3