From 9b4b33ac37494d0d7ae510478981c8a5b77af1d0 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 11 Jan 2020 13:49:59 -0500 Subject: sb/intel/i82371eb: Add PIIX4 definitions These new definitions will be used by two other changes. Change-Id: I242244c444f36af188c871dce037a7a9250206cd Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38367 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82371eb/i82371eb.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/southbridge/intel/i82371eb') diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 2b530102e3..a566af7767 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -40,6 +40,11 @@ int smbus_read_byte(u8 device, u8 address); #define XBCS 0x4e /* X-Bus chip select register */ #define GENCFG 0xb0 /* General configuration register */ +#define GPO2223 (1<<28) /* GPO22/23 */ +#define RTCCFG 0xcb /* Real time clock configuration register */ +#define RTC_POS_DECODE (1<<5) +#define UPPER_RAM_EN (1<<2) +#define RTC_ENABLE (1<<0) /* IDE */ #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ -- cgit v1.2.3