From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i82371eb/Makefile.inc | 16 +- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82371eb/early_pm.c | 51 +++++ src/southbridge/intel/i82371eb/early_smbus.c | 60 ++++++ src/southbridge/intel/i82371eb/enable_rom.c | 49 +++++ src/southbridge/intel/i82371eb/fadt.c | 222 +++++++++++++++++++++ src/southbridge/intel/i82371eb/i82371eb_early_pm.c | 51 ----- .../intel/i82371eb/i82371eb_early_smbus.c | 60 ------ .../intel/i82371eb/i82371eb_enable_rom.c | 49 ----- src/southbridge/intel/i82371eb/i82371eb_fadt.c | 222 --------------------- src/southbridge/intel/i82371eb/i82371eb_ide.c | 201 ------------------- src/southbridge/intel/i82371eb/i82371eb_isa.c | 147 -------------- src/southbridge/intel/i82371eb/i82371eb_reset.c | 30 --- src/southbridge/intel/i82371eb/i82371eb_smbus.c | 137 ------------- src/southbridge/intel/i82371eb/i82371eb_smbus.h | 115 ----------- src/southbridge/intel/i82371eb/i82371eb_usb.c | 66 ------ src/southbridge/intel/i82371eb/ide.c | 201 +++++++++++++++++++ src/southbridge/intel/i82371eb/isa.c | 147 ++++++++++++++ src/southbridge/intel/i82371eb/reset.c | 30 +++ src/southbridge/intel/i82371eb/smbus.c | 137 +++++++++++++ src/southbridge/intel/i82371eb/smbus.h | 115 +++++++++++ src/southbridge/intel/i82371eb/usb.c | 66 ++++++ 22 files changed, 1087 insertions(+), 1087 deletions(-) create mode 100644 src/southbridge/intel/i82371eb/early_pm.c create mode 100644 src/southbridge/intel/i82371eb/early_smbus.c create mode 100644 src/southbridge/intel/i82371eb/enable_rom.c create mode 100644 src/southbridge/intel/i82371eb/fadt.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_early_pm.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_early_smbus.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_enable_rom.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_fadt.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_ide.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_isa.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_reset.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_smbus.c delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_smbus.h delete mode 100644 src/southbridge/intel/i82371eb/i82371eb_usb.c create mode 100644 src/southbridge/intel/i82371eb/ide.c create mode 100644 src/southbridge/intel/i82371eb/isa.c create mode 100644 src/southbridge/intel/i82371eb/reset.c create mode 100644 src/southbridge/intel/i82371eb/smbus.c create mode 100644 src/southbridge/intel/i82371eb/smbus.h create mode 100644 src/southbridge/intel/i82371eb/usb.c (limited to 'src/southbridge/intel/i82371eb') diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index b5ac581ff1..6b27af3c4a 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -19,13 +19,13 @@ ## driver-y += i82371eb.c -driver-y += i82371eb_isa.c -driver-y += i82371eb_ide.c -driver-y += i82371eb_usb.c -driver-y += i82371eb_smbus.c -driver-y += i82371eb_reset.c -driver-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c +driver-y += isa.c +driver-y += ide.c +driver-y += usb.c +driver-y += smbus.c +driver-y += reset.c +driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c -romstage-y += i82371eb_early_pm.c -romstage-y += i82371eb_early_smbus.c +romstage-y += early_pm.c +romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index c818691639..f83b4073c1 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" +#include "southbridge/intel/i82371eb/enable_rom.c" static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c new file mode 100644 index 0000000000..5e52985428 --- /dev/null +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "i82371eb.h" + +void enable_pm(void) +{ + device_t dev; + u8 reg8; + u16 reg16; + + /* Get the SMBus/PM device of the 82371AB/EB/MB. */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); + + /* Set the PM I/O base. */ + pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1); + + /* Enable access to the PM I/O space. */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_IO; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* PM I/O Space Enable (PMIOSE). */ + reg8 = pci_read_config8(dev, PMREGMISC); + reg8 |= PMIOSE; + pci_write_config8(dev, PMREGMISC, reg8); +} diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c new file mode 100644 index 0000000000..d11b06c4f1 --- /dev/null +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "i82371eb.h" +#include "smbus.h" + +void enable_smbus(void) +{ + device_t dev; + u8 reg8; + u16 reg16; + + /* Get the SMBus/PM device of the 82371AB/EB/MB. */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); + + /* Set the SMBus I/O base. */ + pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); + + /* Enable the SMBus controller host interface. */ + reg8 = pci_read_config8(dev, SMBHSTCFG); + reg8 |= SMB_HST_EN; + pci_write_config8(dev, SMBHSTCFG, reg8); + + /* Enable access to the SMBus I/O space. */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_IO; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* Clear any lingering errors, so the transaction will run. */ + outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS); +} + +int smbus_read_byte(u8 device, u8 address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} diff --git a/src/southbridge/intel/i82371eb/enable_rom.c b/src/southbridge/intel/i82371eb/enable_rom.c new file mode 100644 index 0000000000..46b0144f28 --- /dev/null +++ b/src/southbridge/intel/i82371eb/enable_rom.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "i82371eb.h" + +static void i82371eb_enable_rom(void) +{ + u16 reg16; + device_t dev; + + /* + * Note: The Intel 82371AB/EB/MB ISA device can be on different + * PCI bus:device.function locations on different boards. + * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. + * But scanning for the PCI IDs (instead of hardcoding + * bus/device/function numbers) works on all boards. + */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); + + /* Enable access to the whole ROM, disable ROM write access. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= LOWER_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE_1MB; + reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ + pci_write_config16(dev, XBCS, reg16); +} diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c new file mode 100644 index 0000000000..5891440d2e --- /dev/null +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Based on src/southbridge/via/vt8237r/vt8237_fadt.c + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007, 2009 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "i82371eb.h" + +/** + * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. + * Reference: ACPIspec40a, 5.2.9, page 118 + */ +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + device_t dev; + + /* Power management controller */ + dev = dev_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, "CORE ", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 42; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + fadt->preferred_pm_profile = 0; /* unspecified */ + fadt->sci_int = 9; + fadt->smi_cmd = 0; /* smi command port */ + fadt->acpi_enable = 0; /* acpi enable smi command */ + fadt->acpi_disable = 0; /* acpi disable smi command */ + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = DEFAULT_PMBASE; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; + fadt->pm1b_cnt_blk = 0x0; + + fadt->pm2_cnt_blk = 0; + fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR; + fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS; + fadt->gpe1_blk = 0x0; + fadt->gpe1_base = 0; + fadt->gpe1_blk_len = 0; + + /* *_len define register width in bytes */ + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; /* not supported */ + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + + fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ + fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ + fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ + fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */ + fadt->flush_stride = 0; + fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ + fadt->duty_width = 3; /* this width is in bits */ + fadt->day_alrm = 0x0d; /* rtc cmos ram offset */ + fadt->mon_alrm = 0x0; /* not supported */ + fadt->century = 0x0; /* not supported */ + /* + * bit meaning + * 0 1: We have user-visible legacy devices + * 1 1: 8042 + * 2 0: VGA is ok to probe + * 3 1: MSI are not supported + */ + fadt->iapc_boot_arch = 0xb; + /* + * bit meaning + * 0 WBINVD + * Processors in new ACPI-compatible systems are required to + * support this function and indicate this to OSPM by setting + * this field. + * 1 WBINVD_FLUSH + * If set, indicates that the hardware flushes all caches on the + * WBINVD instruction and maintains memory coherency, but does + * not guarantee the caches are invalidated. + * 2 PROC_C1 + * C1 power state (x86 hlt instruction) is supported on all cpus + * 3 P_LVL2_UP + * 0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor + * 4 PWR_BUTTON + * 0: pwr button is fixed feature + * 1: pwr button has control method device if present + * 5 SLP_BUTTON + * 0: sleep button is fixed feature + * 1: sleep button has control method device if present + * 6 FIX_RTC + * 0: RTC wake status supported in fixed register spce + * 7 RTC_S4 + * 1: RTC can wake from S4 + * 8 TMR_VAL_EXT + * 1: pmtimer is 32bit, 0: pmtimer is 24bit + * 9 DCK_CAP + * 1: system supports docking station + * 10 RESET_REG_SUPPORT + * 1: fadt describes reset register for system reset + * 11 SEALED_CASE + * 1: No expansion possible, sealed case + * 12 HEADLESS + * 1: Video output, keyboard and mouse are not connected + * 13 CPU_SW_SLP + * 1: Special processor instruction needs to be executed + * after writing SLP_TYP + * 14 PCI_EXP_WAK + * 1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set + * on platforms with pci express support + * 15 USE_PLATFORM_CLOCK + * 1: OS should prefer platform clock over processor internal + * clock. + * 16 S4_RTC_STS_VALID + * 17 REMOTE_POWER_ON_CAPABLE + * 1: platform correctly supports OSPM leaving GPE wake events + * armed prior to an S5 transition. + * 18 FORCE_APIC_CLUSTER_MODEL + * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE + */ + fadt->flags = 0xa5; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + fadt->reset_value = 0; + + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c deleted file mode 100644 index 5e52985428..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include "i82371eb.h" - -void enable_pm(void) -{ - device_t dev; - u8 reg8; - u16 reg16; - - /* Get the SMBus/PM device of the 82371AB/EB/MB. */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); - - /* Set the PM I/O base. */ - pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1); - - /* Enable access to the PM I/O space. */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_IO; - pci_write_config16(dev, PCI_COMMAND, reg16); - - /* PM I/O Space Enable (PMIOSE). */ - reg8 = pci_read_config8(dev, PMREGMISC); - reg8 |= PMIOSE; - pci_write_config8(dev, PMREGMISC, reg8); -} diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c deleted file mode 100644 index 8505762933..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include "i82371eb.h" -#include "i82371eb_smbus.h" - -void enable_smbus(void) -{ - device_t dev; - u8 reg8; - u16 reg16; - - /* Get the SMBus/PM device of the 82371AB/EB/MB. */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); - - /* Set the SMBus I/O base. */ - pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); - - /* Enable the SMBus controller host interface. */ - reg8 = pci_read_config8(dev, SMBHSTCFG); - reg8 |= SMB_HST_EN; - pci_write_config8(dev, SMBHSTCFG, reg8); - - /* Enable access to the SMBus I/O space. */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_IO; - pci_write_config16(dev, PCI_COMMAND, reg16); - - /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS); -} - -int smbus_read_byte(u8 device, u8 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c deleted file mode 100644 index 46b0144f28..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "i82371eb.h" - -static void i82371eb_enable_rom(void) -{ - u16 reg16; - device_t dev; - - /* - * Note: The Intel 82371AB/EB/MB ISA device can be on different - * PCI bus:device.function locations on different boards. - * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. - * But scanning for the PCI IDs (instead of hardcoding - * bus/device/function numbers) works on all boards. - */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); - - /* Enable access to the whole ROM, disable ROM write access. */ - reg16 = pci_read_config16(dev, XBCS); - reg16 |= LOWER_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE_1MB; - reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ - pci_write_config16(dev, XBCS, reg16); -} diff --git a/src/southbridge/intel/i82371eb/i82371eb_fadt.c b/src/southbridge/intel/i82371eb/i82371eb_fadt.c deleted file mode 100644 index 5891440d2e..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_fadt.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Based on src/southbridge/via/vt8237r/vt8237_fadt.c - * - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2009 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "i82371eb.h" - -/** - * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. - * Reference: ACPIspec40a, 5.2.9, page 118 - */ -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - device_t dev; - - /* Power management controller */ - dev = dev_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 1; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 42; - - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; - fadt->preferred_pm_profile = 0; /* unspecified */ - fadt->sci_int = 9; - fadt->smi_cmd = 0; /* smi command port */ - fadt->acpi_enable = 0; /* acpi enable smi command */ - fadt->acpi_disable = 0; /* acpi disable smi command */ - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - - fadt->pm1a_evt_blk = DEFAULT_PMBASE; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; - fadt->pm1b_cnt_blk = 0x0; - - fadt->pm2_cnt_blk = 0; - fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR; - fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS; - fadt->gpe1_blk = 0x0; - fadt->gpe1_base = 0; - fadt->gpe1_blk_len = 0; - - /* *_len define register width in bytes */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; /* not supported */ - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - - fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ - fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ - fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ - fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */ - fadt->flush_stride = 0; - fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ - fadt->duty_width = 3; /* this width is in bits */ - fadt->day_alrm = 0x0d; /* rtc cmos ram offset */ - fadt->mon_alrm = 0x0; /* not supported */ - fadt->century = 0x0; /* not supported */ - /* - * bit meaning - * 0 1: We have user-visible legacy devices - * 1 1: 8042 - * 2 0: VGA is ok to probe - * 3 1: MSI are not supported - */ - fadt->iapc_boot_arch = 0xb; - /* - * bit meaning - * 0 WBINVD - * Processors in new ACPI-compatible systems are required to - * support this function and indicate this to OSPM by setting - * this field. - * 1 WBINVD_FLUSH - * If set, indicates that the hardware flushes all caches on the - * WBINVD instruction and maintains memory coherency, but does - * not guarantee the caches are invalidated. - * 2 PROC_C1 - * C1 power state (x86 hlt instruction) is supported on all cpus - * 3 P_LVL2_UP - * 0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor - * 4 PWR_BUTTON - * 0: pwr button is fixed feature - * 1: pwr button has control method device if present - * 5 SLP_BUTTON - * 0: sleep button is fixed feature - * 1: sleep button has control method device if present - * 6 FIX_RTC - * 0: RTC wake status supported in fixed register spce - * 7 RTC_S4 - * 1: RTC can wake from S4 - * 8 TMR_VAL_EXT - * 1: pmtimer is 32bit, 0: pmtimer is 24bit - * 9 DCK_CAP - * 1: system supports docking station - * 10 RESET_REG_SUPPORT - * 1: fadt describes reset register for system reset - * 11 SEALED_CASE - * 1: No expansion possible, sealed case - * 12 HEADLESS - * 1: Video output, keyboard and mouse are not connected - * 13 CPU_SW_SLP - * 1: Special processor instruction needs to be executed - * after writing SLP_TYP - * 14 PCI_EXP_WAK - * 1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set - * on platforms with pci express support - * 15 USE_PLATFORM_CLOCK - * 1: OS should prefer platform clock over processor internal - * clock. - * 16 S4_RTC_STS_VALID - * 17 REMOTE_POWER_ON_CAPABLE - * 1: platform correctly supports OSPM leaving GPE wake events - * armed prior to an S5 transition. - * 18 FORCE_APIC_CLUSTER_MODEL - * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE - */ - fadt->flags = 0xa5; - - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 0; - - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/southbridge/intel/i82371eb/i82371eb_ide.c b/src/southbridge/intel/i82371eb/i82371eb_ide.c deleted file mode 100644 index f72bcb63c6..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_ide.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* TODO: Check if this really works for all of the southbridges. */ - -#include -#include -#include -#include -#include -#include "i82371eb.h" - -/** - * Initialize the IDE controller. - * - * Depending on the configuration variables 'ide0_enable' and 'ide1_enable' - * enable or disable the primary and secondary IDE interface, respectively. - * - * Depending on the configuration variable 'ide_legacy_enable' enable or - * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O - * registers (this is required for e.g. FILO). - * - * @param dev The device to use. - */ -static void ide_init_enable(struct device *dev) -{ - u16 reg16; - struct southbridge_intel_i82371eb_config *conf = dev->chip_info; - - /* Enable/disable the primary IDE interface. */ - reg16 = pci_read_config16(dev, IDETIM_PRI); - reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE); - pci_write_config16(dev, IDETIM_PRI, reg16); - printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", - conf->ide0_enable ? "on" : "off"); - - /* Enable/disable the secondary IDE interface. */ - reg16 = pci_read_config16(dev, IDETIM_SEC); - reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE); - pci_write_config16(dev, IDETIM_SEC, reg16); - printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", - conf->ide1_enable ? "on" : "off"); - - /* Enable access to the legacy IDE ports (both primary and secondary), - * and the PCI Bus Master IDE I/O registers. - * Only do this if at least one IDE interface is enabled. - */ - if (conf->ide0_enable || conf->ide1_enable) { - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 = ONOFF(conf->ide_legacy_enable, reg16, - (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); - pci_write_config16(dev, PCI_COMMAND, reg16); - printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n", - conf->ide_legacy_enable ? "on" : "off"); - } -} - -/** - * Initialize the Ultra DMA/33 support of the IDE controller. - * - * Depending on the configuration variables 'ide0_drive0_udma33_enable', - * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and - * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for - * the respective IDE controller and drive. - * - * Only do that if the respective controller is actually enabled, of course. - * - * @param dev The device to use. - */ -static void ide_init_udma33(struct device *dev) -{ - u8 reg8; - struct southbridge_intel_i82371eb_config *conf = dev->chip_info; - - /* Enable/disable UDMA/33 operation (primary IDE interface). */ - if (conf->ide0_enable) { - reg8 = pci_read_config8(dev, UDMACTL); - reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0); - reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1); - pci_write_config8(dev, UDMACTL, reg8); - - printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", - "Primary IDE interface", 0, - conf->ide0_drive0_udma33_enable ? "on" : "off"); - printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", - "Primary IDE interface", 1, - conf->ide0_drive1_udma33_enable ? "on" : "off"); - } - - /* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */ - if (conf->ide1_enable) { - reg8 = pci_read_config8(dev, UDMACTL); - reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0); - reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1); - pci_write_config8(dev, UDMACTL, reg8); - - printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", - "Secondary IDE interface", 0, - conf->ide1_drive0_udma33_enable ? "on" : "off"); - printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", - "Secondary IDE interface", 1, - conf->ide1_drive1_udma33_enable ? "on" : "off"); - } -} - -/** - * IDE init for the Intel 82371FB/SB IDE controller. - * - * These devices do not support UDMA/33, so don't attempt to enable it. - * - * @param dev The device to use. - */ -static void ide_init_i82371fb_sb(struct device *dev) -{ - ide_init_enable(dev); -} - -/** - * IDE init for the Intel 82371AB/EB/MB IDE controller. - * - * @param dev The device to use. - */ -static void ide_init_i82371ab_eb_mb(struct device *dev) -{ - ide_init_enable(dev); - ide_init_udma33(dev); -} - -/* Intel 82371FB/SB */ -static const struct device_operations ide_ops_fb_sb = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init_i82371fb_sb, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, /* No subsystem IDs on 82371XX! */ -}; - -/* Intel 82371AB/EB/MB */ -static const struct device_operations ide_ops_ab_eb_mb = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init_i82371ab_eb_mb, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, /* No subsystem IDs on 82371XX! */ -}; - -/* Intel 82371FB (PIIX) */ -static const struct pci_driver ide_driver_fb __pci_driver = { - .ops = &ide_ops_fb_sb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, -}; - -/* Intel 82371SB (PIIX3) */ -static const struct pci_driver ide_driver_sb __pci_driver = { - .ops = &ide_ops_fb_sb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, -}; - -/* Intel 82371MX (MPIIX) */ -static const struct pci_driver ide_driver_mx __pci_driver = { - .ops = &ide_ops_fb_sb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, -}; - -/* Intel 82437MX (part of the 430MX chipset) */ -static const struct pci_driver ide_driver_82437mx __pci_driver = { - .ops = &ide_ops_fb_sb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, -}; - -/* Intel 82371AB/EB/MB */ -static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { - .ops = &ide_ops_ab_eb_mb, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371AB_IDE, -}; diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c deleted file mode 100644 index d025bf2393..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_isa.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "i82371eb.h" - -#if CONFIG_IOAPIC -static void enable_intel_82093aa_ioapic(void) -{ - u16 reg16; - u32 reg32; - u8 ioapic_id = 2; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - device_t dev; - - dev = dev_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_ISA, 0); - - /* Enable IOAPIC. */ - reg16 = pci_read_config16(dev, XBCS); - reg16 |= (1 << 8); /* APIC Chip Select */ - pci_write_config16(dev, XBCS, reg16); - - /* Set the IOAPIC ID. */ - *ioapic_index = 0; - *ioapic_data = ioapic_id << 24; - - /* Read back and verify the IOAPIC ID. */ - *ioapic_index = 0; - reg32 = (*ioapic_data >> 24) & 0x0f; - printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32); - if (reg32 != ioapic_id) - die("IOAPIC error!\n"); -} -#endif - -static void isa_init(struct device *dev) -{ - u32 reg32; - - /* Initialize the real time clock (RTC). */ - rtc_init(0); - - /* - * Enable special cycles, needed for soft poweroff. - */ - reg32 = pci_read_config16(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SPECIAL; - pci_write_config16(dev, PCI_COMMAND, reg32); - - /* - * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) - * bus, which is a subset of ISA. We select the full ISA bus here. - */ - reg32 = pci_read_config32(dev, GENCFG); - reg32 |= ISA; /* Select ISA, not EIO. */ - pci_write_config16(dev, GENCFG, reg32); - - /* Initialize ISA DMA. */ - isa_dma_init(); - -#if CONFIG_IOAPIC - /* - * Unlike most other southbridges the 82371EB doesn't have a built-in - * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs - * have a discrete IOAPIC (Intel 82093AA) soldered onto the board. - * - * Thus, we can/must only enable the IOAPIC if it actually exists, - * i.e. the respective mainboard does "select IOAPIC". - */ - enable_intel_82093aa_ioapic(); -#endif -} - -static void sb_read_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 2); - res->base = 0xff800000UL; - res->size = 0x00800000UL; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | - IORESOURCE_RESERVE; - -#if CONFIG_IOAPIC - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | - IORESOURCE_RESERVE; -#endif -} - -static const struct device_operations isa_ops = { - .read_resources = sb_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = isa_init, - .scan_bus = scan_static_bus, /* TODO: Needed? */ - .enable = 0, - .ops_pci = 0, /* No subsystem IDs on 82371EB! */ -}; - -static const struct pci_driver isa_driver __pci_driver = { - .ops = &isa_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, -}; - -static const struct pci_driver isa_SB_driver __pci_driver = { - .ops = &isa_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, -}; diff --git a/src/southbridge/intel/i82371eb/i82371eb_reset.c b/src/southbridge/intel/i82371eb/i82371eb_reset.c deleted file mode 100644 index baff05b143..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_reset.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "i82371eb.h" - -/** - * Initiate a hard reset. - */ -void i82371eb_hard_reset(void) -{ - outb(SRST | RCPU, RC); -} diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c deleted file mode 100644 index 4dfd2f4caf..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * Copyright (C) 2010 Keith Hui - * Copyright (C) 2010 Idwer Vollering - * Copyright (C) 2010 Tobias Diedrich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include "i82371eb.h" -#include "i82371eb_smbus.h" - -static void pwrmgt_enable(struct device *dev) -{ - struct southbridge_intel_i82371eb_config *sb = dev->chip_info; - u32 reg, gpo = sb->gpo; - - /* Sets the base address of power management ports. */ - pci_write_config16(dev, PMBA, DEFAULT_PMBASE | 1); - - /* Set Power Management IO Space Enable bit */ - u8 val = pci_read_config8(dev, PMREGMISC); - pci_write_config8(dev, PMREGMISC, val | 1); - - /* set global control: - * bit25 (lid_pol): 1=invert lid polarity - * bit24 (sm_freeze): 1=freeze idle and standby timers - * bit16 (end of smi): 0=disable smi assertion (cleared by hw) - * bits8-15,26: global standby timer inital count 127 * 4minutes - * bit2 (thrm_pol): 1=active low THRM# - * bit0 (smi_en): 1=disable smi generation upon smi event - */ - reg = (sb->lid_polarity<<25)| - (1<<24)| - (0xff<<8)| - (sb->thrm_polarity<<2); - outl(reg, DEFAULT_PMBASE + GLBCTL); - - /* set processor control: - * bit12 (stpclk_en): 1=enable stopping of host clk on lvl3 - * bit11 (sleep_en): 1=enable slp# assertion on lvl3 - * bit9 (cc_en): 1=enable clk control with lvl2 and lvl3 regs - */ - outl(0, DEFAULT_PMBASE + PCNTRL); - - /* disable smi event enables */ - outw(0, DEFAULT_PMBASE + GLBEN); - outl(0, DEFAULT_PMBASE + DEVCTL); - - /* set default gpo value. - * power-on default is 0x7fffbfffh */ - if (gpo) { - /* only 8bit access allowed */ - outb( gpo & 0xff, DEFAULT_PMBASE + GPO0); - outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); - outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); - outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); - } else { - printk(BIOS_SPEW, - "%s: gpo default missing in devicetree.cb!\n", __func__); - } - - /* Clear status events. */ - outw(0xffff, DEFAULT_PMBASE + PMSTS); - outw(0xffff, DEFAULT_PMBASE + GPSTS); - outw(0xffff, DEFAULT_PMBASE + GLBSTS); - outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); - - /* set pmcntrl default */ - outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); -} - -static void pwrmgt_read_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - res = new_resource(dev, 1); - res->base = DEFAULT_PMBASE; - res->size = 0x0040; - res->limit = 0xffff; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | - IORESOURCE_RESERVE; - - res = new_resource(dev, 2); - res->base = SMBUS_IO_BASE; - res->size = 0x0010; - res->limit = 0xffff; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | - IORESOURCE_RESERVE; -} - - -static const struct smbus_bus_operations lops_smbus_bus = { -}; - -static const struct device_operations smbus_ops = { - .read_resources = pwrmgt_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = pwrmgt_enable, - .ops_pci = 0, /* No subsystem IDs on 82371EB! */ - .ops_smbus_bus = &lops_smbus_bus, -}; - -/* Note: There's no SMBus on 82371FB/SB/MX and 82437MX. */ - -/* Intel 82371AB/EB/MB */ -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, -}; diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h deleted file mode 100644 index f82f2edc73..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h +++ /dev/null @@ -1,115 +0,0 @@ -#include -#include "i82371eb.h" - -#define SMBHST_STATUS 0x0 -#define SMBHST_CTL 0x2 -#define SMBHST_CMD 0x3 -#define SMBHST_ADDR 0x4 -#define SMBHST_DAT 0x5 - -#define SMBUS_TIMEOUT (100*1000*10) -#define SMBUS_STATUS_MASK 0x1e -#define SMBUS_ERROR_FLAG (1<<2) - -int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address); - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); - outb(0x80, 0x80); - outb(0x80, 0x80); - outb(0x80, 0x80); - outb(0x80, 0x80); - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHST_STATUS); - if ((val & 0x1) == 0) { - break; - } -#if 0 - if(loops == (SMBUS_TIMEOUT / 2)) { - outw(inw(smbus_io_base + SMBHST_STATUS), - smbus_io_base + SMBHST_STATUS); - } -#endif - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned short val; - smbus_delay(); - - val = inb(smbus_io_base + SMBHST_STATUS); - // Make sure the command is done - if ((val & 0x1) != 0) { - continue; - } - // Don't break out until one of the interrupt - // flags is set. - if (val & 0xfe) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; -} - -int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) -{ - unsigned status_register; - unsigned byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - - /* clear any lingering errors, so the transaction will run */ - outb(0x1e, smbus_io_base + SMBHST_STATUS); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR); - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHST_CMD); - - /* clear the data word...*/ - outb(0, smbus_io_base + SMBHST_DAT); - - /* start a byte read with interrupts disabled */ - outb( (0x02 << 2)|(1<<6), smbus_io_base + SMBHST_CTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - status_register = inw(smbus_io_base + SMBHST_STATUS); - - /* read results of transaction */ - byte = inw(smbus_io_base + SMBHST_DAT) & 0xff; - - if (status_register & 0x04) { -#if 0 - print_debug("Read fail "); - print_debug_hex16(status_register); - print_debug("\n"); -#endif - return SMBUS_ERROR; - } - return byte; -} - diff --git a/src/southbridge/intel/i82371eb/i82371eb_usb.c b/src/southbridge/intel/i82371eb/i82371eb_usb.c deleted file mode 100644 index 1a903a95b0..0000000000 --- a/src/southbridge/intel/i82371eb/i82371eb_usb.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "i82371eb.h" - -/** - * Initialize the USB (UHCI) controller. - * - * Depending on the configuration variable 'usb_enable', enable or - * disable the USB (UHCI) controller. - * - * @param dev The device to use. - */ -static void usb_init(struct device *dev) -{ - /* TODO: No special init needed? */ -} - -static const struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, /* No subsystem IDs on 82371EB! */ -}; - -/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */ - -/* Intel 82371SB (PIIX3) */ -static const struct pci_driver usb_driver_sb __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371SB_USB, -}; - -/* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */ -/* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */ -static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371AB_USB, -}; diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c new file mode 100644 index 0000000000..f72bcb63c6 --- /dev/null +++ b/src/southbridge/intel/i82371eb/ide.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* TODO: Check if this really works for all of the southbridges. */ + +#include +#include +#include +#include +#include +#include "i82371eb.h" + +/** + * Initialize the IDE controller. + * + * Depending on the configuration variables 'ide0_enable' and 'ide1_enable' + * enable or disable the primary and secondary IDE interface, respectively. + * + * Depending on the configuration variable 'ide_legacy_enable' enable or + * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O + * registers (this is required for e.g. FILO). + * + * @param dev The device to use. + */ +static void ide_init_enable(struct device *dev) +{ + u16 reg16; + struct southbridge_intel_i82371eb_config *conf = dev->chip_info; + + /* Enable/disable the primary IDE interface. */ + reg16 = pci_read_config16(dev, IDETIM_PRI); + reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDETIM_PRI, reg16); + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", + conf->ide0_enable ? "on" : "off"); + + /* Enable/disable the secondary IDE interface. */ + reg16 = pci_read_config16(dev, IDETIM_SEC); + reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDETIM_SEC, reg16); + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", + conf->ide1_enable ? "on" : "off"); + + /* Enable access to the legacy IDE ports (both primary and secondary), + * and the PCI Bus Master IDE I/O registers. + * Only do this if at least one IDE interface is enabled. + */ + if (conf->ide0_enable || conf->ide1_enable) { + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 = ONOFF(conf->ide_legacy_enable, reg16, + (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); + pci_write_config16(dev, PCI_COMMAND, reg16); + printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n", + conf->ide_legacy_enable ? "on" : "off"); + } +} + +/** + * Initialize the Ultra DMA/33 support of the IDE controller. + * + * Depending on the configuration variables 'ide0_drive0_udma33_enable', + * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and + * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for + * the respective IDE controller and drive. + * + * Only do that if the respective controller is actually enabled, of course. + * + * @param dev The device to use. + */ +static void ide_init_udma33(struct device *dev) +{ + u8 reg8; + struct southbridge_intel_i82371eb_config *conf = dev->chip_info; + + /* Enable/disable UDMA/33 operation (primary IDE interface). */ + if (conf->ide0_enable) { + reg8 = pci_read_config8(dev, UDMACTL); + reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0); + reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1); + pci_write_config8(dev, UDMACTL, reg8); + + printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", + "Primary IDE interface", 0, + conf->ide0_drive0_udma33_enable ? "on" : "off"); + printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", + "Primary IDE interface", 1, + conf->ide0_drive1_udma33_enable ? "on" : "off"); + } + + /* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */ + if (conf->ide1_enable) { + reg8 = pci_read_config8(dev, UDMACTL); + reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0); + reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1); + pci_write_config8(dev, UDMACTL, reg8); + + printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", + "Secondary IDE interface", 0, + conf->ide1_drive0_udma33_enable ? "on" : "off"); + printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", + "Secondary IDE interface", 1, + conf->ide1_drive1_udma33_enable ? "on" : "off"); + } +} + +/** + * IDE init for the Intel 82371FB/SB IDE controller. + * + * These devices do not support UDMA/33, so don't attempt to enable it. + * + * @param dev The device to use. + */ +static void ide_init_i82371fb_sb(struct device *dev) +{ + ide_init_enable(dev); +} + +/** + * IDE init for the Intel 82371AB/EB/MB IDE controller. + * + * @param dev The device to use. + */ +static void ide_init_i82371ab_eb_mb(struct device *dev) +{ + ide_init_enable(dev); + ide_init_udma33(dev); +} + +/* Intel 82371FB/SB */ +static const struct device_operations ide_ops_fb_sb = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init_i82371fb_sb, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + +/* Intel 82371AB/EB/MB */ +static const struct device_operations ide_ops_ab_eb_mb = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init_i82371ab_eb_mb, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + +/* Intel 82371FB (PIIX) */ +static const struct pci_driver ide_driver_fb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, +}; + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver ide_driver_sb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, +}; + +/* Intel 82371MX (MPIIX) */ +static const struct pci_driver ide_driver_mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, +}; + +/* Intel 82437MX (part of the 430MX chipset) */ +static const struct pci_driver ide_driver_82437mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, +}; + +/* Intel 82371AB/EB/MB */ +static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { + .ops = &ide_ops_ab_eb_mb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_IDE, +}; diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c new file mode 100644 index 0000000000..d025bf2393 --- /dev/null +++ b/src/southbridge/intel/i82371eb/isa.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "i82371eb.h" + +#if CONFIG_IOAPIC +static void enable_intel_82093aa_ioapic(void) +{ + u16 reg16; + u32 reg32; + u8 ioapic_id = 2; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + device_t dev; + + dev = dev_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_ISA, 0); + + /* Enable IOAPIC. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= (1 << 8); /* APIC Chip Select */ + pci_write_config16(dev, XBCS, reg16); + + /* Set the IOAPIC ID. */ + *ioapic_index = 0; + *ioapic_data = ioapic_id << 24; + + /* Read back and verify the IOAPIC ID. */ + *ioapic_index = 0; + reg32 = (*ioapic_data >> 24) & 0x0f; + printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32); + if (reg32 != ioapic_id) + die("IOAPIC error!\n"); +} +#endif + +static void isa_init(struct device *dev) +{ + u32 reg32; + + /* Initialize the real time clock (RTC). */ + rtc_init(0); + + /* + * Enable special cycles, needed for soft poweroff. + */ + reg32 = pci_read_config16(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SPECIAL; + pci_write_config16(dev, PCI_COMMAND, reg32); + + /* + * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) + * bus, which is a subset of ISA. We select the full ISA bus here. + */ + reg32 = pci_read_config32(dev, GENCFG); + reg32 |= ISA; /* Select ISA, not EIO. */ + pci_write_config16(dev, GENCFG, reg32); + + /* Initialize ISA DMA. */ + isa_dma_init(); + +#if CONFIG_IOAPIC + /* + * Unlike most other southbridges the 82371EB doesn't have a built-in + * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs + * have a discrete IOAPIC (Intel 82093AA) soldered onto the board. + * + * Thus, we can/must only enable the IOAPIC if it actually exists, + * i.e. the respective mainboard does "select IOAPIC". + */ + enable_intel_82093aa_ioapic(); +#endif +} + +static void sb_read_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 2); + res->base = 0xff800000UL; + res->size = 0x00800000UL; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | + IORESOURCE_RESERVE; + +#if CONFIG_IOAPIC + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | + IORESOURCE_RESERVE; +#endif +} + +static const struct device_operations isa_ops = { + .read_resources = sb_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = isa_init, + .scan_bus = scan_static_bus, /* TODO: Needed? */ + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371EB! */ +}; + +static const struct pci_driver isa_driver __pci_driver = { + .ops = &isa_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, +}; + +static const struct pci_driver isa_SB_driver __pci_driver = { + .ops = &isa_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, +}; diff --git a/src/southbridge/intel/i82371eb/reset.c b/src/southbridge/intel/i82371eb/reset.c new file mode 100644 index 0000000000..baff05b143 --- /dev/null +++ b/src/southbridge/intel/i82371eb/reset.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "i82371eb.h" + +/** + * Initiate a hard reset. + */ +void i82371eb_hard_reset(void) +{ + outb(SRST | RCPU, RC); +} diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c new file mode 100644 index 0000000000..b1a51c6a8a --- /dev/null +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * Copyright (C) 2010 Keith Hui + * Copyright (C) 2010 Idwer Vollering + * Copyright (C) 2010 Tobias Diedrich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "i82371eb.h" +#include "smbus.h" + +static void pwrmgt_enable(struct device *dev) +{ + struct southbridge_intel_i82371eb_config *sb = dev->chip_info; + u32 reg, gpo = sb->gpo; + + /* Sets the base address of power management ports. */ + pci_write_config16(dev, PMBA, DEFAULT_PMBASE | 1); + + /* Set Power Management IO Space Enable bit */ + u8 val = pci_read_config8(dev, PMREGMISC); + pci_write_config8(dev, PMREGMISC, val | 1); + + /* set global control: + * bit25 (lid_pol): 1=invert lid polarity + * bit24 (sm_freeze): 1=freeze idle and standby timers + * bit16 (end of smi): 0=disable smi assertion (cleared by hw) + * bits8-15,26: global standby timer inital count 127 * 4minutes + * bit2 (thrm_pol): 1=active low THRM# + * bit0 (smi_en): 1=disable smi generation upon smi event + */ + reg = (sb->lid_polarity<<25)| + (1<<24)| + (0xff<<8)| + (sb->thrm_polarity<<2); + outl(reg, DEFAULT_PMBASE + GLBCTL); + + /* set processor control: + * bit12 (stpclk_en): 1=enable stopping of host clk on lvl3 + * bit11 (sleep_en): 1=enable slp# assertion on lvl3 + * bit9 (cc_en): 1=enable clk control with lvl2 and lvl3 regs + */ + outl(0, DEFAULT_PMBASE + PCNTRL); + + /* disable smi event enables */ + outw(0, DEFAULT_PMBASE + GLBEN); + outl(0, DEFAULT_PMBASE + DEVCTL); + + /* set default gpo value. + * power-on default is 0x7fffbfffh */ + if (gpo) { + /* only 8bit access allowed */ + outb( gpo & 0xff, DEFAULT_PMBASE + GPO0); + outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); + outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); + outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); + } else { + printk(BIOS_SPEW, + "%s: gpo default missing in devicetree.cb!\n", __func__); + } + + /* Clear status events. */ + outw(0xffff, DEFAULT_PMBASE + PMSTS); + outw(0xffff, DEFAULT_PMBASE + GPSTS); + outw(0xffff, DEFAULT_PMBASE + GLBSTS); + outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); + + /* set pmcntrl default */ + outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); +} + +static void pwrmgt_read_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = DEFAULT_PMBASE; + res->size = 0x0040; + res->limit = 0xffff; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | + IORESOURCE_RESERVE; + + res = new_resource(dev, 2); + res->base = SMBUS_IO_BASE; + res->size = 0x0010; + res->limit = 0xffff; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | + IORESOURCE_RESERVE; +} + + +static const struct smbus_bus_operations lops_smbus_bus = { +}; + +static const struct device_operations smbus_ops = { + .read_resources = pwrmgt_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .enable = pwrmgt_enable, + .ops_pci = 0, /* No subsystem IDs on 82371EB! */ + .ops_smbus_bus = &lops_smbus_bus, +}; + +/* Note: There's no SMBus on 82371FB/SB/MX and 82437MX. */ + +/* Intel 82371AB/EB/MB */ +static const struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, +}; diff --git a/src/southbridge/intel/i82371eb/smbus.h b/src/southbridge/intel/i82371eb/smbus.h new file mode 100644 index 0000000000..f82f2edc73 --- /dev/null +++ b/src/southbridge/intel/i82371eb/smbus.h @@ -0,0 +1,115 @@ +#include +#include "i82371eb.h" + +#define SMBHST_STATUS 0x0 +#define SMBHST_CTL 0x2 +#define SMBHST_CMD 0x3 +#define SMBHST_ADDR 0x4 +#define SMBHST_DAT 0x5 + +#define SMBUS_TIMEOUT (100*1000*10) +#define SMBUS_STATUS_MASK 0x1e +#define SMBUS_ERROR_FLAG (1<<2) + +int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address); + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); + outb(0x80, 0x80); + outb(0x80, 0x80); + outb(0x80, 0x80); + outb(0x80, 0x80); + outb(0x80, 0x80); +} + +static int smbus_wait_until_ready(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(smbus_io_base + SMBHST_STATUS); + if ((val & 0x1) == 0) { + break; + } +#if 0 + if(loops == (SMBUS_TIMEOUT / 2)) { + outw(inw(smbus_io_base + SMBHST_STATUS), + smbus_io_base + SMBHST_STATUS); + } +#endif + } while(--loops); + return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; +} + +static int smbus_wait_until_done(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned short val; + smbus_delay(); + + val = inb(smbus_io_base + SMBHST_STATUS); + // Make sure the command is done + if ((val & 0x1) != 0) { + continue; + } + // Don't break out until one of the interrupt + // flags is set. + if (val & 0xfe) { + break; + } + } while(--loops); + return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; +} + +int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +{ + unsigned status_register; + unsigned byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + + /* clear any lingering errors, so the transaction will run */ + outb(0x1e, smbus_io_base + SMBHST_STATUS); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR); + + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHST_CMD); + + /* clear the data word...*/ + outb(0, smbus_io_base + SMBHST_DAT); + + /* start a byte read with interrupts disabled */ + outb( (0x02 << 2)|(1<<6), smbus_io_base + SMBHST_CTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + status_register = inw(smbus_io_base + SMBHST_STATUS); + + /* read results of transaction */ + byte = inw(smbus_io_base + SMBHST_DAT) & 0xff; + + if (status_register & 0x04) { +#if 0 + print_debug("Read fail "); + print_debug_hex16(status_register); + print_debug("\n"); +#endif + return SMBUS_ERROR; + } + return byte; +} + diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c new file mode 100644 index 0000000000..1a903a95b0 --- /dev/null +++ b/src/southbridge/intel/i82371eb/usb.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "i82371eb.h" + +/** + * Initialize the USB (UHCI) controller. + * + * Depending on the configuration variable 'usb_enable', enable or + * disable the USB (UHCI) controller. + * + * @param dev The device to use. + */ +static void usb_init(struct device *dev) +{ + /* TODO: No special init needed? */ +} + +static const struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371EB! */ +}; + +/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */ + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver usb_driver_sb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_USB, +}; + +/* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */ +/* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */ +static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_USB, +}; -- cgit v1.2.3