From 7cdcc38f292d7a8ffd285d17c848e60e41eec759 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Mon, 6 Jan 2020 19:00:31 +0200
Subject: sb/intel/common: Add smbus_host_reset()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/i82371eb/early_smbus.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/southbridge/intel/i82371eb')

diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c
index 4168a057ef..917a3b45f1 100644
--- a/src/southbridge/intel/i82371eb/early_smbus.c
+++ b/src/southbridge/intel/i82371eb/early_smbus.c
@@ -15,12 +15,11 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
+#include <console/console.h>
 #include <device/pci_ops.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
-#include <southbridge/intel/common/smbus.h>
 #include <device/smbus_host.h>
 #include "i82371eb.h"
 
@@ -47,8 +46,9 @@ void enable_smbus(void)
 	reg16 |= PCI_COMMAND_IO;
 	pci_write_config16(dev, PCI_COMMAND, reg16);
 
-	/* Clear any lingering errors, so the transaction will run. */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+	smbus_host_reset(SMBUS_IO_BASE);
+
+	printk(BIOS_DEBUG, "SMBus controller enabled\n");
 }
 
 int smbus_read_byte(u8 device, u8 address)
-- 
cgit v1.2.3