From 79572e4f32f844f60338d1aafdba6b94f4111a5c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 13 Jul 2020 00:17:43 +0200 Subject: src: Make HAVE_CF9_RESET set the FADT reset register All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Frans Hendriks --- src/southbridge/intel/i82371eb/fadt.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'src/southbridge/intel/i82371eb') diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 249b22b5bc..05581f43b2 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -101,15 +101,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) * 18 FORCE_APIC_CLUSTER_MODEL * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE */ - fadt->flags |= 0xa5 | ACPI_FADT_RESET_REGISTER; - - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 0x06; + fadt->flags |= 0xa5; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; -- cgit v1.2.3