From 67c48a36776695b956ea49eb308c1025e430b475 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 14 Apr 2023 10:20:03 +0300 Subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After the obsoletion of Processor() it is necessary to provide _CST package to define P_LVLx IO addresses for C2/C3 transitions. The latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/southbridge/intel/i82371eb/fadt.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/southbridge/intel/i82371eb') diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index fc3258ae9b..681d09ca95 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -36,8 +36,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ -- cgit v1.2.3