From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i3100/Makefile.inc | 16 +- src/southbridge/intel/i3100/early_lpc.c | 46 +++ src/southbridge/intel/i3100/early_smbus.c | 43 +++ src/southbridge/intel/i3100/ehci.c | 68 ++++ src/southbridge/intel/i3100/i3100_early_lpc.c | 46 --- src/southbridge/intel/i3100/i3100_early_smbus.c | 43 --- src/southbridge/intel/i3100/i3100_ehci.c | 68 ---- src/southbridge/intel/i3100/i3100_lpc.c | 433 ----------------------- src/southbridge/intel/i3100/i3100_pci.c | 46 --- src/southbridge/intel/i3100/i3100_pciexp_portb.c | 94 ----- src/southbridge/intel/i3100/i3100_reset.c | 27 -- src/southbridge/intel/i3100/i3100_sata.c | 129 ------- src/southbridge/intel/i3100/i3100_smbus.c | 79 ----- src/southbridge/intel/i3100/i3100_smbus.h | 112 ------ src/southbridge/intel/i3100/i3100_uhci.c | 68 ---- src/southbridge/intel/i3100/lpc.c | 433 +++++++++++++++++++++++ src/southbridge/intel/i3100/pci.c | 46 +++ src/southbridge/intel/i3100/pciexp_portb.c | 94 +++++ src/southbridge/intel/i3100/reset.c | 27 ++ src/southbridge/intel/i3100/sata.c | 129 +++++++ src/southbridge/intel/i3100/smbus.c | 79 +++++ src/southbridge/intel/i3100/smbus.h | 112 ++++++ src/southbridge/intel/i3100/uhci.c | 68 ++++ 23 files changed, 1153 insertions(+), 1153 deletions(-) create mode 100644 src/southbridge/intel/i3100/early_lpc.c create mode 100644 src/southbridge/intel/i3100/early_smbus.c create mode 100644 src/southbridge/intel/i3100/ehci.c delete mode 100644 src/southbridge/intel/i3100/i3100_early_lpc.c delete mode 100644 src/southbridge/intel/i3100/i3100_early_smbus.c delete mode 100644 src/southbridge/intel/i3100/i3100_ehci.c delete mode 100644 src/southbridge/intel/i3100/i3100_lpc.c delete mode 100644 src/southbridge/intel/i3100/i3100_pci.c delete mode 100644 src/southbridge/intel/i3100/i3100_pciexp_portb.c delete mode 100644 src/southbridge/intel/i3100/i3100_reset.c delete mode 100644 src/southbridge/intel/i3100/i3100_sata.c delete mode 100644 src/southbridge/intel/i3100/i3100_smbus.c delete mode 100644 src/southbridge/intel/i3100/i3100_smbus.h delete mode 100644 src/southbridge/intel/i3100/i3100_uhci.c create mode 100644 src/southbridge/intel/i3100/lpc.c create mode 100644 src/southbridge/intel/i3100/pci.c create mode 100644 src/southbridge/intel/i3100/pciexp_portb.c create mode 100644 src/southbridge/intel/i3100/reset.c create mode 100644 src/southbridge/intel/i3100/sata.c create mode 100644 src/southbridge/intel/i3100/smbus.c create mode 100644 src/southbridge/intel/i3100/smbus.h create mode 100644 src/southbridge/intel/i3100/uhci.c (limited to 'src/southbridge/intel/i3100') diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc index dcc1fb7357..fa6caf1b52 100644 --- a/src/southbridge/intel/i3100/Makefile.inc +++ b/src/southbridge/intel/i3100/Makefile.inc @@ -1,9 +1,9 @@ driver-y += i3100.c -driver-y += i3100_uhci.c -driver-y += i3100_lpc.c -driver-y += i3100_sata.c -driver-y += i3100_ehci.c -driver-y += i3100_smbus.c -driver-y += i3100_pci.c -ramstage-y += i3100_reset.c -ramstage-y += i3100_pciexp_portb.c +driver-y += uhci.c +driver-y += lpc.c +driver-y += sata.c +driver-y += ehci.c +driver-y += smbus.c +driver-y += pci.c +ramstage-y += reset.c +ramstage-y += pciexp_portb.c diff --git a/src/southbridge/intel/i3100/early_lpc.c b/src/southbridge/intel/i3100/early_lpc.c new file mode 100644 index 0000000000..3397aff1f8 --- /dev/null +++ b/src/southbridge/intel/i3100/early_lpc.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +static void i3100_enable_superio(void) +{ + device_t dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Enable decoding of I/O locations for SuperIO devices */ + pci_write_config16(dev, 0x80, 0x0010); + pci_write_config16(dev, 0x82, 0x340f); + + /* Enable the SERIRQs (start pulse width is 8 clock cycles) */ + pci_write_config8(dev, 0x64, 0xD2); +} + +static void i3100_halt_tco_timer(void) +{ + device_t dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Temporarily enable the ACPI I/O range at 0x4000 */ + pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); + pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); + + /* Halt the TCO timer, preventing SMI and automatic reboot */ + outw(inw(0x4068) | (1 << 11), 0x4068); + + /* Disable the ACPI I/O range */ + pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7)); +} diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c new file mode 100644 index 0000000000..f3d4450c5e --- /dev/null +++ b/src/southbridge/intel/i3100/early_smbus.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "smbus.h" + +#define SMBUS_IO_BASE 0x0f00 + +static void enable_smbus(void) +{ + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + + print_spew("SMBus controller enabled\n"); + pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + pci_write_config8(dev, 0x40, 1); + pci_write_config8(dev, 0x4, 1); + /* SMBALERT_DIS */ + outb(4, SMBUS_IO_BASE + SMBSLVCMD); + + /* Disable interrupt generation */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); +} + +static int smbus_read_byte(u32 device, u32 address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} diff --git a/src/southbridge/intel/i3100/ehci.c b/src/southbridge/intel/i3100/ehci.c new file mode 100644 index 0000000000..195ea99cd1 --- /dev/null +++ b/src/southbridge/intel/i3100/ehci.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include "i3100.h" + +static void ehci_init(struct device *dev) +{ +} + +static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + u8 access_cntl; + access_cntl = pci_read_config8(dev, 0x80); + /* Enable writes to protected registers */ + pci_write_config8(dev, 0x80, access_cntl | 1); + /* Write the subsystem vendor and device id */ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + /* Restore protection */ + pci_write_config8(dev, 0x80, access_cntl); +} + +static struct pci_operations lops_pci = { + .set_subsystem = &ehci_set_subsystem, +}; +static struct device_operations ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ehci_init, + .scan_bus = 0, + .enable = i3100_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ehci_driver __pci_driver = { + .ops = &ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_EHCI, +}; + +static const struct pci_driver ehci_driver_ep80579 __pci_driver = { + .ops = &ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_EHCI, +}; diff --git a/src/southbridge/intel/i3100/i3100_early_lpc.c b/src/southbridge/intel/i3100/i3100_early_lpc.c deleted file mode 100644 index 3397aff1f8..0000000000 --- a/src/southbridge/intel/i3100/i3100_early_lpc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -static void i3100_enable_superio(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Enable decoding of I/O locations for SuperIO devices */ - pci_write_config16(dev, 0x80, 0x0010); - pci_write_config16(dev, 0x82, 0x340f); - - /* Enable the SERIRQs (start pulse width is 8 clock cycles) */ - pci_write_config8(dev, 0x64, 0xD2); -} - -static void i3100_halt_tco_timer(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Temporarily enable the ACPI I/O range at 0x4000 */ - pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); - pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); - - /* Halt the TCO timer, preventing SMI and automatic reboot */ - outw(inw(0x4068) | (1 << 11), 0x4068); - - /* Disable the ACPI I/O range */ - pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7)); -} diff --git a/src/southbridge/intel/i3100/i3100_early_smbus.c b/src/southbridge/intel/i3100/i3100_early_smbus.c deleted file mode 100644 index 79825d153a..0000000000 --- a/src/southbridge/intel/i3100/i3100_early_smbus.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -#include "i3100_smbus.h" - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - print_spew("SMBus controller enabled\n"); - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - pci_write_config8(dev, 0x40, 1); - pci_write_config8(dev, 0x4, 1); - /* SMBALERT_DIS */ - outb(4, SMBUS_IO_BASE + SMBSLVCMD); - - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); -} - -static int smbus_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i3100/i3100_ehci.c b/src/southbridge/intel/i3100/i3100_ehci.c deleted file mode 100644 index 195ea99cd1..0000000000 --- a/src/southbridge/intel/i3100/i3100_ehci.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -#include -#include -#include -#include -#include -#include "i3100.h" - -static void ehci_init(struct device *dev) -{ -} - -static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - u8 access_cntl; - access_cntl = pci_read_config8(dev, 0x80); - /* Enable writes to protected registers */ - pci_write_config8(dev, 0x80, access_cntl | 1); - /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - /* Restore protection */ - pci_write_config8(dev, 0x80, access_cntl); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &ehci_set_subsystem, -}; -static struct device_operations ehci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ehci_driver __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_EHCI, -}; - -static const struct pci_driver ehci_driver_ep80579 __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_EHCI, -}; diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c deleted file mode 100644 index 1544ecd44f..0000000000 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Linux Networx - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -/* This code is based on src/southbridge/intel/esb6300/esb6300_lpc.c */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "i3100.h" - -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x48 -#define RCBA 0xf0 - -#define SERIRQ_CNTL 0x64 - -#define GEN_PMCON_1 0xA0 -#define GEN_PMCON_2 0xA2 -#define GEN_PMCON_3 0xA4 - -#define NMI_OFF 0 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -static void i3100_enable_serial_irqs(device_t dev) -{ - /* set packet length and toggle silent mode bit */ - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); -} - -typedef struct southbridge_intel_i3100_config config_t; - -static void set_i3100_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_use_sel, gpio_use_sel2; - int i; - - gpio_use_sel = inl(res->base + 0x00) | 0x0000c603; - gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100; - for (i = 0; i < 64; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_USE_MASK) { - case I3100_GPIO_USE_AS_NATIVE: - val = 0; - break; - case I3100_GPIO_USE_AS_GPIO: - val = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_use_sel &= ~(1 << i); - gpio_use_sel |= (val << i); - } else { - gpio_use_sel2 &= ~(1 << (i - 32)); - gpio_use_sel2 |= (val << (i - 32)); - } - } - outl(gpio_use_sel, res->base + 0x00); - outl(gpio_use_sel2, res->base + 0x30); -} - -static void set_i3100_gpio_direction( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_io_sel, gpio_io_sel2; - int i; - - gpio_io_sel = inl(res->base + 0x04); - gpio_io_sel2 = inl(res->base + 0x34); - for (i = 0; i < 64; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_SEL_MASK) { - case I3100_GPIO_SEL_OUTPUT: - val = 0; - break; - case I3100_GPIO_SEL_INPUT: - val = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_io_sel &= ~(1 << i); - gpio_io_sel |= (val << i); - } else { - gpio_io_sel2 &= ~(1 << (i - 32)); - gpio_io_sel2 |= (val << (i - 32)); - } - } - outl(gpio_io_sel, res->base + 0x04); - outl(gpio_io_sel2, res->base + 0x34); -} - -static void set_i3100_gpio_level( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_lvl, gpio_lvl2; - u32 gpio_blink; - int i; - - gpio_lvl = inl(res->base + 0x0c); - gpio_blink = inl(res->base + 0x18); - gpio_lvl2 = inl(res->base + 0x38); - for (i = 0; i < 64; i++) { - int val, blink; - switch (config->gpio[i] & I3100_GPIO_LVL_MASK) { - case I3100_GPIO_LVL_LOW: - val = 0; - blink = 0; - break; - case I3100_GPIO_LVL_HIGH: - val = 1; - blink = 0; - break; - case I3100_GPIO_LVL_BLINK: - val = 1; - blink = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_lvl &= ~(1 << i); - gpio_blink &= ~(1 << i); - gpio_lvl |= (val << i); - gpio_blink |= (blink << i); - } else { - gpio_lvl2 &= ~(1 << (i - 32)); - gpio_lvl2 |= (val << (i - 32)); - } - } - outl(gpio_lvl, res->base + 0x0c); - outl(gpio_blink, res->base + 0x18); - outl(gpio_lvl2, res->base + 0x38); -} - -static void set_i3100_gpio_inv( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_inv; - int i; - - gpio_inv = inl(res->base + 0x2c); - for (i = 0; i < 32; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_INV_MASK) { - case I3100_GPIO_INV_OFF: - val = 0; - break; - case I3100_GPIO_INV_ON: - val = 1; - break; - default: - continue; - } - gpio_inv &= ~(1 << i); - gpio_inv |= (val << i); - } - outl(gpio_inv, res->base + 0x2c); -} - -static void i3100_pirq_init(device_t dev) -{ - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if(config->pirq_a_d) { - pci_write_config32(dev, 0x60, config->pirq_a_d); - } - if(config->pirq_e_h) { - pci_write_config32(dev, 0x68, config->pirq_e_h); - } -} - -static void i3100_power_options(device_t dev) { - u8 reg8; - u16 reg16; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - int nmi_option; - - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - get_option(&pwr_on, "power_on_after_fail"); - reg8 = pci_read_config8(dev, GEN_PMCON_3); - reg8 &= 0xfe; - if (pwr_on) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - /* avoid #S4 assertions */ - reg8 |= (3 << 4); - /* minimum asssertion is 1 to 2 RTCCLK */ - reg8 &= ~(1 << 3); - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); - - /* Set up NMI on errors. */ - reg8 = inb(0x61); - /* Higher Nibble must be 0 */ - reg8 &= 0x0f; - /* IOCHK# NMI Enable */ - reg8 &= ~(1 << 3); - /* PCI SERR# Enable */ - // reg8 &= ~(1 << 2); - /* PCI SERR# Disable for now */ - reg8 |= (1 << 2); - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - /* Set NMI. */ - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); - } else { - /* Can't mask NMI from PCI-E and NMI_NOW */ - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); - } - outb(reg8, 0x70); - - // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~((3 << 0) | (1 << 10)); - reg16 |= (1 << 3) | (1 << 5); - /* CLKRUN_EN */ - // reg16 |= (1 << 2); - pci_write_config16(dev, GEN_PMCON_1, reg16); - - // Set the board's GPI routing. - // i82801gx_gpi_routing(dev); -} - -static void i3100_gpio_init(device_t dev) -{ - struct resource *res; - config_t *config; - - /* Skip if I don't have any configuration */ - if (!dev->chip_info) { - return; - } - /* The programmer is responsible for ensuring - * a valid gpio configuration. - */ - - /* Get the chip configuration */ - config = dev->chip_info; - /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); - if (!res) { - return; - } - - /* Set the use selects */ - set_i3100_gpio_use_sel(dev, res, config); - - /* Set the IO direction */ - set_i3100_gpio_direction(dev, res, config); - - /* Setup the input inverters */ - set_i3100_gpio_inv(dev, res, config); - - /* Set the value on the GPIO output pins */ - set_i3100_gpio_level(dev, res, config); - -} - - -static void lpc_init(struct device *dev) -{ - struct resource *res; - - /* Enable IO APIC */ - res = find_resource(dev, RCBA); - if (!res) { - return; - } - *((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0); - - // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode - // (register 0x10/0x11) while the old code used int 1 (register 0x12) - // ... Why? - setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID - - /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */ - pci_write_config32(dev, 0xd0, 0x00000000); - - i3100_enable_serial_irqs(dev); - - /* Set up the PIRQ */ - i3100_pirq_init(dev); - - /* Setup power options */ - i3100_power_options(dev); - - /* Set the state of the gpio lines */ - i3100_gpio_init(dev); - - /* Initialize the real time clock */ - rtc_init(0); - - /* Initialize isa dma */ - isa_dma_init(); -} - -static void i3100_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); - - /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add resource for RCBA */ - res = new_resource(dev, RCBA); - res->size = 0x4000; - res->limit = 0xffffc000; - res->align = 14; - res->gran = 14; - res->flags = IORESOURCE_MEM; -} - -static void i3100_lpc_enable_resources(device_t dev) -{ - u8 acpi_cntl, gpio_cntl; - - /* Enable the normal pci resources */ - pci_dev_enable_resources(dev); - - /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 7); - pci_write_config8(dev, 0x44, acpi_cntl); - - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x4c); - gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x4c, gpio_cntl); - - /* Enable the RCBA */ - pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations lpc_ops = { - .read_resources = i3100_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = i3100_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_LPC, -}; - -static const struct pci_driver lpc_driver_ep80579 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_LPC, -}; diff --git a/src/southbridge/intel/i3100/i3100_pci.c b/src/southbridge/intel/i3100/i3100_pci.c deleted file mode 100644 index 99fc95d0f6..0000000000 --- a/src/southbridge/intel/i3100/i3100_pci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -#include -#include -#include -#include -#include -#include "i3100.h" - -static void pci_init(struct device *dev) -{ -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCI, -}; - diff --git a/src/southbridge/intel/i3100/i3100_pciexp_portb.c b/src/southbridge/intel/i3100/i3100_pciexp_portb.c deleted file mode 100644 index 31502a46de..0000000000 --- a/src/southbridge/intel/i3100/i3100_pciexp_portb.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */ - -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include - -#define PCIE_LCTL 0x50 -#define PCIE_LSTS 0x52 - -typedef struct northbridge_intel_i3100_config config_t; - -static void pcie_init(struct device *dev) -{ -} - -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) -{ - u16 val; - u16 ctl; - int flag = 0; - do { - val = pci_read_config16(dev, PCIE_LSTS); - printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val); - if ((val & (1<<10)) && (!flag)) { /* training error */ - ctl = pci_read_config16(dev, PCIE_LCTL); - pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5))); - val = pci_read_config16(dev, PCIE_LSTS); - printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val); - flag=1; - hard_reset(); - } - } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0, -}; - -static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1, -}; - -static const struct pci_driver pci_driver_2 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2, -}; - -static const struct pci_driver pci_driver_3 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3, -}; diff --git a/src/southbridge/intel/i3100/i3100_reset.c b/src/southbridge/intel/i3100/i3100_reset.c deleted file mode 100644 index 3f35f5fb83..0000000000 --- a/src/southbridge/intel/i3100/i3100_reset.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -#include -#include - -void hard_reset(void) -{ - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/i3100/i3100_sata.c b/src/southbridge/intel/i3100/i3100_sata.c deleted file mode 100644 index af22600f90..0000000000 --- a/src/southbridge/intel/i3100/i3100_sata.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -/* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */ - -#include -#include -#include -#include -#include -#include "i3100.h" - -typedef struct southbridge_intel_i3100_config config_t; - -static void sata_init(struct device *dev) -{ - u8 ahci; - - /* Get the chip configuration */ - ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03; - - /* Enable SATA devices */ - printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); - - if(ahci) { - /* AHCI mode */ - pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0)); - - /* Enable ports */ - pci_write_config8(dev, SATA_PCS, 0x03); - pci_write_config8(dev, SATA_PCS + 1, 0x0F); - - /* Setup timings */ - pci_write_config16(dev, SATA_PTIM, 0x8000); - pci_write_config16(dev, SATA_STIM, 0x8000); - - /* Synchronous DMA */ - pci_write_config8(dev, SATA_SYNCC, 0); - pci_write_config16(dev, SATA_SYNCTIM, 0); - - /* IDE I/O configuration */ - pci_write_config32(dev, SATA_IIOC, 0); - - } else { - /* SATA configuration */ - pci_write_config8(dev, SATA_CMD, 0x07); - pci_write_config8(dev, SATA_PI, 0x8f); - - /* Set timings */ - pci_write_config16(dev, SATA_PTIM, 0x0a307); - pci_write_config16(dev, SATA_STIM, 0x0a307); - - /* Sync DMA */ - pci_write_config8(dev, SATA_SYNCC, 0x0f); - pci_write_config16(dev, SATA_SYNCTIM, 0x1111); - - /* Fast ATA */ - pci_write_config16(dev, SATA_IIOC, 0x1000); - - /* Select IDE mode */ - pci_write_config8(dev, SATA_MAP, 0x00); - - /* Enable ports 0-3 */ - pci_write_config8(dev, SATA_PCS + 1, 0x0f); - - } - printk(BIOS_DEBUG, "SATA Enabled\n"); -} - -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = sata_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_IDE, -}; - -static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_AHCI, -}; - -static const struct pci_driver ide_driver_ep80579 __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_IDE, -}; - -static const struct pci_driver sata_driver_ep80579 __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI, -}; diff --git a/src/southbridge/intel/i3100/i3100_smbus.c b/src/southbridge/intel/i3100/i3100_smbus.c deleted file mode 100644 index f51363d92a..0000000000 --- a/src/southbridge/intel/i3100/i3100_smbus.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include "i3100.h" -#include "i3100_smbus.h" - -static int lsmbus_read_byte(device_t dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_read_byte(res->base, device, address); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, -}; - -static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &smbus_set_subsystem, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = i3100_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_SMB, -}; - -static const struct pci_driver smbus_driver_ep80579 __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_SMB, -}; diff --git a/src/southbridge/intel/i3100/i3100_smbus.h b/src/southbridge/intel/i3100/i3100_smbus.h deleted file mode 100644 index 7023a5b751..0000000000 --- a/src/southbridge/intel/i3100/i3100_smbus.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This code is based on src/southbridge/intel/esb6300/esb6300_smbus.h */ - -#include - -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf -#define SMBSLVCMD 0x11 - -#define SMBUS_TIMEOUT (100*1000*10) - -static void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(u32 smbus_io_base) -{ - u32 loops = SMBUS_TIMEOUT; - u8 byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while (byte & 1); - return loops ? 0 : -1; -} - -static int smbus_wait_until_done(u32 smbus_io_base) -{ - u32 loops = SMBUS_TIMEOUT; - u8 byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while ((byte & 1) || (byte & ~((1 << 6)|(1 << 0))) == 0); - return loops ? 0 : -1; -} - -static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address) -{ - u8 global_status_register; - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - /* setup transaction */ - /* disable interrupts */ - outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, smbus_io_base + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL); - /* clear any lingering errors, so the transaction will run */ - outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, smbus_io_base + SMBHSTDAT0); - - /* start the command */ - outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT); - - /* Ignore the In Use Status... */ - global_status_register &= ~(3 << 5); - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} diff --git a/src/southbridge/intel/i3100/i3100_uhci.c b/src/southbridge/intel/i3100/i3100_uhci.c deleted file mode 100644 index 5453509769..0000000000 --- a/src/southbridge/intel/i3100/i3100_uhci.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -#include -#include -#include -#include -#include -#include "i3100.h" - -static void uhci_init(struct device *dev) -{ -} - -static void uhci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &uhci_set_subsystem, -}; - -static struct device_operations uhci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = uhci_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver uhci_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_UHCI, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_UHCI2, -}; - -static const struct pci_driver uhci_driver_ep80579 __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_UHCI, -}; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c new file mode 100644 index 0000000000..1544ecd44f --- /dev/null +++ b/src/southbridge/intel/i3100/lpc.c @@ -0,0 +1,433 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Linux Networx + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* This code is based on src/southbridge/intel/esb6300/esb6300_lpc.c */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "i3100.h" + +#define ACPI_BAR 0x40 +#define GPIO_BAR 0x48 +#define RCBA 0xf0 + +#define SERIRQ_CNTL 0x64 + +#define GEN_PMCON_1 0xA0 +#define GEN_PMCON_2 0xA2 +#define GEN_PMCON_3 0xA4 + +#define NMI_OFF 0 +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +static void i3100_enable_serial_irqs(device_t dev) +{ + /* set packet length and toggle silent mode bit */ + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); +} + +typedef struct southbridge_intel_i3100_config config_t; + +static void set_i3100_gpio_use_sel( + device_t dev, struct resource *res, config_t *config) +{ + u32 gpio_use_sel, gpio_use_sel2; + int i; + + gpio_use_sel = inl(res->base + 0x00) | 0x0000c603; + gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100; + for (i = 0; i < 64; i++) { + int val; + switch (config->gpio[i] & I3100_GPIO_USE_MASK) { + case I3100_GPIO_USE_AS_NATIVE: + val = 0; + break; + case I3100_GPIO_USE_AS_GPIO: + val = 1; + break; + default: + continue; + } + /* The caller is responsible for not playing with unimplemented bits */ + if (i < 32) { + gpio_use_sel &= ~(1 << i); + gpio_use_sel |= (val << i); + } else { + gpio_use_sel2 &= ~(1 << (i - 32)); + gpio_use_sel2 |= (val << (i - 32)); + } + } + outl(gpio_use_sel, res->base + 0x00); + outl(gpio_use_sel2, res->base + 0x30); +} + +static void set_i3100_gpio_direction( + device_t dev, struct resource *res, config_t *config) +{ + u32 gpio_io_sel, gpio_io_sel2; + int i; + + gpio_io_sel = inl(res->base + 0x04); + gpio_io_sel2 = inl(res->base + 0x34); + for (i = 0; i < 64; i++) { + int val; + switch (config->gpio[i] & I3100_GPIO_SEL_MASK) { + case I3100_GPIO_SEL_OUTPUT: + val = 0; + break; + case I3100_GPIO_SEL_INPUT: + val = 1; + break; + default: + continue; + } + /* The caller is responsible for not playing with unimplemented bits */ + if (i < 32) { + gpio_io_sel &= ~(1 << i); + gpio_io_sel |= (val << i); + } else { + gpio_io_sel2 &= ~(1 << (i - 32)); + gpio_io_sel2 |= (val << (i - 32)); + } + } + outl(gpio_io_sel, res->base + 0x04); + outl(gpio_io_sel2, res->base + 0x34); +} + +static void set_i3100_gpio_level( + device_t dev, struct resource *res, config_t *config) +{ + u32 gpio_lvl, gpio_lvl2; + u32 gpio_blink; + int i; + + gpio_lvl = inl(res->base + 0x0c); + gpio_blink = inl(res->base + 0x18); + gpio_lvl2 = inl(res->base + 0x38); + for (i = 0; i < 64; i++) { + int val, blink; + switch (config->gpio[i] & I3100_GPIO_LVL_MASK) { + case I3100_GPIO_LVL_LOW: + val = 0; + blink = 0; + break; + case I3100_GPIO_LVL_HIGH: + val = 1; + blink = 0; + break; + case I3100_GPIO_LVL_BLINK: + val = 1; + blink = 1; + break; + default: + continue; + } + /* The caller is responsible for not playing with unimplemented bits */ + if (i < 32) { + gpio_lvl &= ~(1 << i); + gpio_blink &= ~(1 << i); + gpio_lvl |= (val << i); + gpio_blink |= (blink << i); + } else { + gpio_lvl2 &= ~(1 << (i - 32)); + gpio_lvl2 |= (val << (i - 32)); + } + } + outl(gpio_lvl, res->base + 0x0c); + outl(gpio_blink, res->base + 0x18); + outl(gpio_lvl2, res->base + 0x38); +} + +static void set_i3100_gpio_inv( + device_t dev, struct resource *res, config_t *config) +{ + u32 gpio_inv; + int i; + + gpio_inv = inl(res->base + 0x2c); + for (i = 0; i < 32; i++) { + int val; + switch (config->gpio[i] & I3100_GPIO_INV_MASK) { + case I3100_GPIO_INV_OFF: + val = 0; + break; + case I3100_GPIO_INV_ON: + val = 1; + break; + default: + continue; + } + gpio_inv &= ~(1 << i); + gpio_inv |= (val << i); + } + outl(gpio_inv, res->base + 0x2c); +} + +static void i3100_pirq_init(device_t dev) +{ + config_t *config; + + /* Get the chip configuration */ + config = dev->chip_info; + + if(config->pirq_a_d) { + pci_write_config32(dev, 0x60, config->pirq_a_d); + } + if(config->pirq_e_h) { + pci_write_config32(dev, 0x68, config->pirq_e_h); + } +} + +static void i3100_power_options(device_t dev) { + u8 reg8; + u16 reg16; + int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int nmi_option; + + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + get_option(&pwr_on, "power_on_after_fail"); + reg8 = pci_read_config8(dev, GEN_PMCON_3); + reg8 &= 0xfe; + if (pwr_on) { + reg8 &= ~1; + } else { + reg8 |= 1; + } + /* avoid #S4 assertions */ + reg8 |= (3 << 4); + /* minimum asssertion is 1 to 2 RTCCLK */ + reg8 &= ~(1 << 3); + pci_write_config8(dev, GEN_PMCON_3, reg8); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + /* Higher Nibble must be 0 */ + reg8 &= 0x0f; + /* IOCHK# NMI Enable */ + reg8 &= ~(1 << 3); + /* PCI SERR# Enable */ + // reg8 &= ~(1 << 2); + /* PCI SERR# Disable for now */ + reg8 |= (1 << 2); + outb(reg8, 0x61); + + reg8 = inb(0x70); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + /* Set NMI. */ + printk(BIOS_INFO, "NMI sources enabled.\n"); + reg8 &= ~(1 << 7); + } else { + /* Can't mask NMI from PCI-E and NMI_NOW */ + printk(BIOS_INFO, "NMI sources disabled.\n"); + reg8 |= ( 1 << 7); + } + outb(reg8, 0x70); + + // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 &= ~((3 << 0) | (1 << 10)); + reg16 |= (1 << 3) | (1 << 5); + /* CLKRUN_EN */ + // reg16 |= (1 << 2); + pci_write_config16(dev, GEN_PMCON_1, reg16); + + // Set the board's GPI routing. + // i82801gx_gpi_routing(dev); +} + +static void i3100_gpio_init(device_t dev) +{ + struct resource *res; + config_t *config; + + /* Skip if I don't have any configuration */ + if (!dev->chip_info) { + return; + } + /* The programmer is responsible for ensuring + * a valid gpio configuration. + */ + + /* Get the chip configuration */ + config = dev->chip_info; + /* Find the GPIO bar */ + res = find_resource(dev, GPIO_BAR); + if (!res) { + return; + } + + /* Set the use selects */ + set_i3100_gpio_use_sel(dev, res, config); + + /* Set the IO direction */ + set_i3100_gpio_direction(dev, res, config); + + /* Setup the input inverters */ + set_i3100_gpio_inv(dev, res, config); + + /* Set the value on the GPIO output pins */ + set_i3100_gpio_level(dev, res, config); + +} + + +static void lpc_init(struct device *dev) +{ + struct resource *res; + + /* Enable IO APIC */ + res = find_resource(dev, RCBA); + if (!res) { + return; + } + *((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0); + + // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode + // (register 0x10/0x11) while the old code used int 1 (register 0x12) + // ... Why? + setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID + + /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */ + pci_write_config32(dev, 0xd0, 0x00000000); + + i3100_enable_serial_irqs(dev); + + /* Set up the PIRQ */ + i3100_pirq_init(dev); + + /* Setup power options */ + i3100_power_options(dev); + + /* Set the state of the gpio lines */ + i3100_gpio_init(dev); + + /* Initialize the real time clock */ + rtc_init(0); + + /* Initialize isa dma */ + isa_dma_init(); +} + +static void i3100_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add the ACPI BAR */ + res = pci_get_resource(dev, ACPI_BAR); + + /* Add the GPIO BAR */ + res = pci_get_resource(dev, GPIO_BAR); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Add resource for RCBA */ + res = new_resource(dev, RCBA); + res->size = 0x4000; + res->limit = 0xffffc000; + res->align = 14; + res->gran = 14; + res->flags = IORESOURCE_MEM; +} + +static void i3100_lpc_enable_resources(device_t dev) +{ + u8 acpi_cntl, gpio_cntl; + + /* Enable the normal pci resources */ + pci_dev_enable_resources(dev); + + /* Enable the ACPI bar */ + acpi_cntl = pci_read_config8(dev, 0x44); + acpi_cntl |= (1 << 7); + pci_write_config8(dev, 0x44, acpi_cntl); + + /* Enable the GPIO bar */ + gpio_cntl = pci_read_config8(dev, 0x4c); + gpio_cntl |= (1 << 4); + pci_write_config8(dev, 0x4c, gpio_cntl); + + /* Enable the RCBA */ + pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations lpc_ops = { + .read_resources = i3100_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = i3100_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i3100_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_LPC, +}; + +static const struct pci_driver lpc_driver_ep80579 __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_LPC, +}; diff --git a/src/southbridge/intel/i3100/pci.c b/src/southbridge/intel/i3100/pci.c new file mode 100644 index 0000000000..99fc95d0f6 --- /dev/null +++ b/src/southbridge/intel/i3100/pci.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include "i3100.h" + +static void pci_init(struct device *dev) +{ +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .ops_pci = 0, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_PCI, +}; + diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c new file mode 100644 index 0000000000..31502a46de --- /dev/null +++ b/src/southbridge/intel/i3100/pciexp_portb.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include + +#define PCIE_LCTL 0x50 +#define PCIE_LSTS 0x52 + +typedef struct northbridge_intel_i3100_config config_t; + +static void pcie_init(struct device *dev) +{ +} + +static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +{ + u16 val; + u16 ctl; + int flag = 0; + do { + val = pci_read_config16(dev, PCIE_LSTS); + printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val); + if ((val & (1<<10)) && (!flag)) { /* training error */ + ctl = pci_read_config16(dev, PCIE_LCTL); + pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5))); + val = pci_read_config16(dev, PCIE_LSTS); + printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val); + flag=1; + hard_reset(); + } + } while (val & (3<<10)); + return pciexp_scan_bridge(dev, max); +} + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pcie_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static const struct pci_driver pci_driver_0 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0, +}; + +static const struct pci_driver pci_driver_1 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1, +}; + +static const struct pci_driver pci_driver_2 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2, +}; + +static const struct pci_driver pci_driver_3 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3, +}; diff --git a/src/southbridge/intel/i3100/reset.c b/src/southbridge/intel/i3100/reset.c new file mode 100644 index 0000000000..3f35f5fb83 --- /dev/null +++ b/src/southbridge/intel/i3100/reset.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include +#include + +void hard_reset(void) +{ + outb(0x06, 0xcf9); +} diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c new file mode 100644 index 0000000000..af22600f90 --- /dev/null +++ b/src/southbridge/intel/i3100/sata.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */ + +#include +#include +#include +#include +#include +#include "i3100.h" + +typedef struct southbridge_intel_i3100_config config_t; + +static void sata_init(struct device *dev) +{ + u8 ahci; + + /* Get the chip configuration */ + ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03; + + /* Enable SATA devices */ + printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); + + if(ahci) { + /* AHCI mode */ + pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0)); + + /* Enable ports */ + pci_write_config8(dev, SATA_PCS, 0x03); + pci_write_config8(dev, SATA_PCS + 1, 0x0F); + + /* Setup timings */ + pci_write_config16(dev, SATA_PTIM, 0x8000); + pci_write_config16(dev, SATA_STIM, 0x8000); + + /* Synchronous DMA */ + pci_write_config8(dev, SATA_SYNCC, 0); + pci_write_config16(dev, SATA_SYNCTIM, 0); + + /* IDE I/O configuration */ + pci_write_config32(dev, SATA_IIOC, 0); + + } else { + /* SATA configuration */ + pci_write_config8(dev, SATA_CMD, 0x07); + pci_write_config8(dev, SATA_PI, 0x8f); + + /* Set timings */ + pci_write_config16(dev, SATA_PTIM, 0x0a307); + pci_write_config16(dev, SATA_STIM, 0x0a307); + + /* Sync DMA */ + pci_write_config8(dev, SATA_SYNCC, 0x0f); + pci_write_config16(dev, SATA_SYNCTIM, 0x1111); + + /* Fast ATA */ + pci_write_config16(dev, SATA_IIOC, 0x1000); + + /* Select IDE mode */ + pci_write_config8(dev, SATA_MAP, 0x00); + + /* Enable ports 0-3 */ + pci_write_config8(dev, SATA_PCS + 1, 0x0f); + + } + printk(BIOS_DEBUG, "SATA Enabled\n"); +} + +static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = sata_set_subsystem, +}; + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .scan_bus = 0, + .enable = i3100_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ide_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_IDE, +}; + +static const struct pci_driver sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_AHCI, +}; + +static const struct pci_driver ide_driver_ep80579 __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_IDE, +}; + +static const struct pci_driver sata_driver_ep80579 __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI, +}; diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c new file mode 100644 index 0000000000..23602acb21 --- /dev/null +++ b/src/southbridge/intel/i3100/smbus.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "i3100.h" +#include "smbus.h" + +static int lsmbus_read_byte(device_t dev, u8 address) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + + return do_smbus_read_byte(res->base, device, address); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .read_byte = lsmbus_read_byte, +}; + +static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = &smbus_set_subsystem, +}; + +static struct device_operations smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .enable = i3100_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; + +static const struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_SMB, +}; + +static const struct pci_driver smbus_driver_ep80579 __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_SMB, +}; diff --git a/src/southbridge/intel/i3100/smbus.h b/src/southbridge/intel/i3100/smbus.h new file mode 100644 index 0000000000..7023a5b751 --- /dev/null +++ b/src/southbridge/intel/i3100/smbus.h @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code is based on src/southbridge/intel/esb6300/esb6300_smbus.h */ + +#include + +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf +#define SMBSLVCMD 0x11 + +#define SMBUS_TIMEOUT (100*1000*10) + +static void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +static int smbus_wait_until_ready(u32 smbus_io_base) +{ + u32 loops = SMBUS_TIMEOUT; + u8 byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +static int smbus_wait_until_done(u32 smbus_io_base) +{ + u32 loops = SMBUS_TIMEOUT; + u8 byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6)|(1 << 0))) == 0); + return loops ? 0 : -1; +} + +static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address) +{ + u8 global_status_register; + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* setup transaction */ + /* disable interrupts */ + outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL); + /* clear any lingering errors, so the transaction will run */ + outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, smbus_io_base + SMBHSTDAT0); + + /* start the command */ + outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT); + + /* Ignore the In Use Status... */ + global_status_register &= ~(3 << 5); + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} diff --git a/src/southbridge/intel/i3100/uhci.c b/src/southbridge/intel/i3100/uhci.c new file mode 100644 index 0000000000..5453509769 --- /dev/null +++ b/src/southbridge/intel/i3100/uhci.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include "i3100.h" + +static void uhci_init(struct device *dev) +{ +} + +static void uhci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = &uhci_set_subsystem, +}; + +static struct device_operations uhci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = uhci_init, + .scan_bus = 0, + .enable = i3100_enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver uhci_driver __pci_driver = { + .ops = &uhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_UHCI, +}; + +static const struct pci_driver usb2_driver __pci_driver = { + .ops = &uhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_UHCI2, +}; + +static const struct pci_driver uhci_driver_ep80579 __pci_driver = { + .ops = &uhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_UHCI, +}; -- cgit v1.2.3