From 264566c177dac98e67c2a4765fe08c5d8de10753 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 15 Oct 2017 15:06:48 -0600 Subject: Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/i3100/early_smbus.c | 44 ------------------------------- 1 file changed, 44 deletions(-) delete mode 100644 src/southbridge/intel/i3100/early_smbus.c (limited to 'src/southbridge/intel/i3100/early_smbus.c') diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c deleted file mode 100644 index 35fe614d8e..0000000000 --- a/src/southbridge/intel/i3100/early_smbus.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - printk(BIOS_SPEW, "SMBus controller enabled\n"); - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - pci_write_config8(dev, 0x40, 1); - pci_write_config8(dev, 0x4, 1); - /* SMBALERT_DIS */ - outb(4, SMBUS_IO_BASE + SMBSLVCMD); - - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); -} - -static __attribute__((unused)) int smbus_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -static __attribute__((unused)) int smbus_write_byte(unsigned device, u8 address, u8 data) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); -} -- cgit v1.2.3