From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/southbridge/intel/fsp_rangeley/soc.c | 4 ++-- src/southbridge/intel/fsp_rangeley/spi.c | 5 ++--- src/southbridge/intel/fsp_rangeley/watchdog.c | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) (limited to 'src/southbridge/intel/fsp_rangeley') diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c index 13b64c4e7f..fd83342ac7 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.c +++ b/src/southbridge/intel/fsp_rangeley/soc.c @@ -29,7 +29,7 @@ int soc_silicon_revision(void) { if (soc_revision_id < 0) soc_revision_id = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pcidev_on_root(0x1f, 0), PCI_REVISION_ID); return soc_revision_id; } @@ -38,7 +38,7 @@ int soc_silicon_type(void) { if (soc_type < 0) soc_type = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pcidev_on_root(0x1f, 0), PCI_DEVICE_ID + 1); return soc_type; } diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 97548069ad..1571925027 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -341,14 +341,13 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - struct device *dev; uint32_t ids; uint16_t vendor_id, device_id; #ifdef __SMM__ - dev = PCI_DEV(0, 31, 0); + pci_devfn_t dev = PCI_DEV(0, 31, 0); #else - dev = dev_find_slot(0, PCI_DEVFN(31, 0)); + struct device *dev = pcidev_on_root(31, 0); #endif pci_read_config_dword(dev, 0, &ids); vendor_id = ids; diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c index ff1c571505..d7d3141e59 100644 --- a/src/southbridge/intel/fsp_rangeley/watchdog.c +++ b/src/southbridge/intel/fsp_rangeley/watchdog.c @@ -29,7 +29,7 @@ void watchdog_off(void) u32 value, abase; /* Turn off the watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Enable I/O space. */ value = pci_read_config16(dev, 0x04); -- cgit v1.2.3