From ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 31 Aug 2016 19:22:16 +0200 Subject: src/southbridge: Code formating Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/southbridge/intel/fsp_rangeley/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/fsp_rangeley/gpio.c') diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index e57d85541e..2a2061cb1a 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* CFIO Core Well Set 1 */ if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) { write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002); - for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { + for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0)) continue; write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0); @@ -78,7 +78,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* CFIO SUS Well Set 1 */ if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) { write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002); - for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { + for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0)) continue; write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0); -- cgit v1.2.3