From c2c634a089fa990418c363e2ff2e5ff70bdd3580 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:37:28 +0100 Subject: nb/sb/cpu: Drop Intel Rangeley support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: David Hendricks --- src/southbridge/intel/fsp_rangeley/chip.h | 84 ------------------------------- 1 file changed, 84 deletions(-) delete mode 100644 src/southbridge/intel/fsp_rangeley/chip.h (limited to 'src/southbridge/intel/fsp_rangeley/chip.h') diff --git a/src/southbridge/intel/fsp_rangeley/chip.h b/src/southbridge/intel/fsp_rangeley/chip.h deleted file mode 100644 index 3eef5a9046..0000000000 --- a/src/southbridge/intel/fsp_rangeley/chip.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H -#define SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H - -#include - -struct southbridge_intel_fsp_rangeley_config { - - /** - * GPI Routing configuration - * - * Only the lower two bits have a meaning: - * 00: No effect - * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - * 10: SCI (if corresponding GPIO_EN bit is also set) - * 11: reserved - */ - uint8_t gpi0_routing; - uint8_t gpi1_routing; - uint8_t gpi2_routing; - uint8_t gpi3_routing; - uint8_t gpi4_routing; - uint8_t gpi5_routing; - uint8_t gpi6_routing; - uint8_t gpi7_routing; - uint8_t gpi8_routing; - uint8_t gpi9_routing; - uint8_t gpi10_routing; - uint8_t gpi11_routing; - uint8_t gpi12_routing; - uint8_t gpi13_routing; - uint8_t gpi14_routing; - uint8_t gpi15_routing; - - uint32_t gpe0_en; - uint16_t alt_gp_smi_en; - - /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; - uint8_t sata_port_map; - uint32_t sata_port0_gen3_tx; - uint32_t sata_port1_gen3_tx; - - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Override PCIe ASPM */ - uint8_t pcie_aspm_f0; - uint8_t pcie_aspm_f1; - uint8_t pcie_aspm_f2; - uint8_t pcie_aspm_f3; - uint8_t pcie_aspm_f4; - uint8_t pcie_aspm_f5; - uint8_t pcie_aspm_f6; - uint8_t pcie_aspm_f7; - - /* ACPI configuration */ - uint8_t fadt_pm_profile; - uint16_t fadt_boot_arch; - -}; - -#endif /* SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H */ -- cgit v1.2.3